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130 Commits

Author SHA1 Message Date
Nelson Chu
50331d64f1 RISC-V: Clarify the addends of pc-relative access. 
The original discussion was here,
https://github.com/riscv/riscv-elf-psabi-doc/issues/184

After discussing with Kito Cheng, I think the addends of %pcrel_hi
and %pcrel_lo are both allowed in GNU toolchain.  However, both of
the them mean the offset of symbols, rather than the pc address.
But the addends of %got_pcrel_hi and it's %pcrel_lo do not look
reasonable.  I believe gcc won't generate the got patterns with
addends, so linker should report dangerous relocation errors,
in case the assembly code use them.

Another issue was here,
https://sourceware.org/pipermail/binutils/2021-June/116983.html

At the beginnig, I suppose %pcrel_hi and %pcrel_lo are valid only
when they are in the same input section.  But Jim Wilson points out
that gcc may generate %hi and %lo in the different input sections,
when -freorder-blocks-and-partition option is used.  So that a memory
references for a loop may have the %hi outside the loop, but the %lo
remain in the loop.  However, it is hard to create the testcases,
to see if %pcrel_hi and %pcrel_lo have the same behavior.

Unfortunately, I notice that the current pcrel resolver cannot
work for the above case.  For now we build a hash table for pcrel
at the start of riscv_elf_relocate_section, and then free the hash
at the end.  But riscv_elf_relocate_section only handles an input
section at a time, so that means we can only resolve the %pcrel_hi
and %pcrel_lo which are in the same input section.  Otherwise, like
the above case, we will report "%pcrel_lo missing matching %pcrel_hi"
for them.  I have no plan to improve this in the short-term, so maybe
we can wait until someone meets the problem before we deal with it.

bfd/
    * elfnn-riscv.c (riscv_pcrel_hi_reloc): Added field to store
    the original relocation type, in case the type is converted to
    R_RISCV_HI20.
    (riscv_pcrel_lo_reloc): Removed unused name field.
    (riscv_pcrel_relocs): Added comments.
    (riscv_zero_pcrel_hi_reloc): Removed unused input_bfd.
    (riscv_record_pcrel_hi_reloc): Updated.
    (riscv_record_pcrel_lo_reloc): Likewise.
    (riscv_resolve_pcrel_lo_relocs): Likewise.  Check the original
    type of auipc, to make sure the %pcrel_lo without any addends.
    Otherwise, report dangerous relocation error.
    (riscv_elf_relocate_section): Updated above functions are changed.
    For R_RISCV_GOT_HI20, report dangerous relocation error when addend
    isn't zero.
ld/
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d: New testcase.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d: New testcase.
    Should report error since the %pcrel_lo with addend refers to
    %got_pcrel_hi.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d: New testcase.
    Should report error since the %got_pcrel_hi with addend.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld: Likewise.
 2021-06-22 17:14:55 +08:00
Nelson Chu
ef9d256562 RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 
2021-05-31  Nelson Chu  <nelson.chu@sifive.com>
            Lifang Xia  <lifang_xia@c-sky.com>

The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro.  It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.

One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations.  I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.

For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:

(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o

After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.

bfd/
    PR 27566
    * elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
    to monitor the data segment phase.
    (bfd_elfNN_riscv_set_data_segment_info): New function called by
    after_allocation, to set the data_segment_phase from expld.dataseg.
    (_bfd_riscv_relax_section): Don't relax when data_segment_phase is
    exp_seg_relro_adjust (0x4).
    * elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
    (bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
    PR 27566
    * emultempl/riscvelf.em (after_allocation): Call
    riscv_set_data_segment_info to set data segment phase before relaxing.
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
    * testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
    * testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
    * testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
    * testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
 2021-05-31 11:29:26 +08:00
Nelson Chu
fe1f847d9a RISC-V: Allow to link the objects with unknown prefixed extensions. 
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, ....  The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.

The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.

bfd/
    * elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
    prefixed extension name if check_unknown_prefixed_ext is false.
    * elfnn-riscv.c (riscv_merge_arch_attr_info): Set
    check_unknown_prefixed_ext to false for linker.
gas/
    * config/tc-riscv.c (riscv_set_arch): Set
    check_unknown_prefixed_ext to true for assembler.
 2021-05-26 11:02:29 +08:00
Nelson Chu
75f03fa774 RISC-V: Check the overflow for %pcrel_lo addend more strictly. 
The %pcrel_lo addend may causes the overflow, and need more than one
%pcrel_hi values.  But there may be only one auipc, shared by those
%pcrel_lo with addends.  However, the existing check method in the
riscv_resolve_pcrel_lo_relocs, may not be able to work for some
special/corner cases.

Consider the testcases pcrel-lo-addend-2b.  Before applying this patch,
I can compile it successfully.  But in fact the addend cause the value
of %pcrel_hi to be different.  This patch try to check the value of
%pcrel_hi directly, to make sure it won't be changed.  Otherwise, linker
will report the following errors,

(.text+0xa): dangerous relocation: %pcrel_lo overflow with an addend,
the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000
after adding the %pcrel_lo addend

The toolchain regressions, rv64gc-linux/rv64gc-elf/rv32gc-linux/rv32i-elf,
pass expectedly and looks fine.

bfd/
    * elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Check the values
    of %pcrel_hi, before and after adding the addend.  Make sure the
    value won't be changed, otherwise, report dangerous error.
ld/
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d: Renamed from
    pcrel-lo-addend-2.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d: New testcase.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s: Likewise.
 2021-05-14 16:14:00 +08:00
Nelson Chu
ddfe525f28 RISC-V: PR27584, surpress local and empty name symbols for nm. 
The local ".L0" symbol are usually generated to mark where the
auipc instruction is, and clang also uses ".LBB" to do the same
thing.  Besides, clang also uses the empty name symbols for label
differences.  Arm surpress their mapping symbols by regarding them
as special symbols, and MIPS surpress all local symbols.  Therefore,
RISC-V probably need to surpress the local and empty name symbols
for nm and related tools.  User can use "--special-syms" to show
these surpressed symbols.

bfd/
    PR27584
    * elfnn-riscv.c (riscv_elf_is_target_special_symbol): Added to
    omit local and empty symbols since they usually generated to
    mark the auipc instructions.
 2021-04-15 10:32:36 +08:00
Nelson Chu
e3839c100f RISC-V: Don't report the mismatched version warning for the implicit extensions. 
bfd/
    * elfnn-riscv.c (riscv_version_mismatch): Do not report the warning
    when the version of input or output is RISCV_UNKNOWN_VERSION, since
    the extension is added implicitly.
    * elfxx-riscv.c: Updated the obsolete comments.
    (RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h.
    * elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
 2021-04-13 12:49:51 +08:00
Alan Modra
83c79df86b C99 bfd configury 
Certain library headers and functions are required by C99.  This
removes configure tests for them.  The patch also removes AC_ISC_POSIX
and AC_HEADER_DIRENT, which the autoconf manual states are obsolescent.
sys/time.h is no longer tangled up with time.h so it can be handled by
the gprof configure.

	* configure.ac: Don't check for long long or long double type.
	Don't check for alloca.h, limits.h, stddef.h, stdlib.h, string.h,
	strings.h, time.h, wchar.h, wctype.h or sys/time.h.  Don't check
	for strtoull, free, malloc, realloc, getenv, strstr, snprintf,
	vsnprintf, strlen or setitimer.  Sort AC_CHECK_DECLS.
	(AC_ISC_POSIX): Don't invoke.
	(AC_HEADER_TIME, AC_HEADER_DIRENT, ACX_HEADER_STRING): Likewise.
	* sysdep.h: Remove many HAVE_*_H checks and fallback declarations.
	Do test HAVE_SYS_TYPES_H.  Don't include sys/time.h.  Reorder
	header order as per automake AC_INCLUDES_DEFAULT.
	* bfd-in.h: Include inttypes.h unconditionally.
	* bfd.c (_bfd_doprnt, _bfd_doprnt_scan): Assume long long and
	long double are available.
	(bfd_scan_vma): Assume long long and strtoull are available.
	* elflink.c: Include limits.h unconditionally.
	* elfnn-riscv.c: Likewise.
	* wasm-module.c: Likewise.
	* hpux-core.c: Include dirent.h unconditionally.
	* trad-core.c: Likewise.
	* hosts/x86-64linux.h: Include stdlib.h unconditionally.
	* peXXigen.c: Remove HAVE_WCHAR_H and HAVE_WCTYPE_H checks.
	* elf32-m68hc1x.c: Don't include alloca-conf.h.
	* elf64-hppa.c: Likewise.
	* som.c: Likewise.
	* wasm-module.c: Likewise.
	* xsym.c: Likewise.
	* bfd-in2.h: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
 2021-04-05 15:27:37 +09:30
Martin Liska
3f3328b816 Use startswith more for strncmp function calls. 
bfd/ChangeLog:

	* elf-bfd.h (bfd_section_is_ctf): Use startswith function.
	* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
	(elf_get_reloc_section): Likewise.
	* elf32-arc.c (elf_arc_size_dynamic_sections): Likewise.
	* elf32-m32r.c (m32r_elf_section_flags): Likewise.
	* elf32-microblaze.c (microblaze_elf_size_dynamic_sections): Likewise.
	* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
	(nds32_elf_relocate_section): Likewise.
	(nds32_elf_action_discarded): Likewise.
	(nds32_elf_check_relocs): Likewise.
	(nds32_elf_section_flags): Likewise.
	* elf32-or1k.c (or1k_elf_check_relocs): Likewise.
	* elf32-ppc.c (ppc_elf_section_from_shdr): Likewise.
	* elf32-rx.c (rx_table_find): Likewise.
	(rx_table_map): Likewise.
	* elf32-spu.c (spu_elf_backend_symbol_processing): Likewise.
	(spu_elf_find_overlays): Likewise.
	(needs_ovl_stub): Likewise.
	(allocate_spuear_stubs): Likewise.
	(build_spuear_stubs): Likewise.
	(mark_overlay_section): Likewise.
	(spu_elf_auto_overlay): Likewise.
	(spu_elf_output_symbol_hook): Likewise.
	* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
	* elf32-xtensa.c (xtensa_property_section_name): Likewise.
	* elf64-ppc.c (ppc64_elf_section_flags): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* elflink.c (resolve_section): Likewise.
	(UNARY_OP): Likewise.
	(BINARY_OP_HEAD): Likewise.
	(elf_link_input_bfd): Likewise.
	* elfnn-riscv.c (riscv_elf_size_dynamic_sections): Likewise.
	* elfxx-riscv.c (riscv_parse_subset): Likewise.
	* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
	* opncls.c (get_build_id): Likewise.

binutils/ChangeLog:

	* dllwrap.c: Use startswith function.
	* objcopy.c (is_dwo_section): Likewise.
	(handle_remove_section_option): Likewise.
	(copy_main): Likewise.
	* objdump.c (is_significant_symbol_name): Likewise.
 2021-04-01 14:59:04 +02:00
Alan Modra
0a1b45a20e Use bool in bfd 
* sysdep.h: POISON_BFD_BOOLEAN: Define.
	* aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h,
	* aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c,
	* bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c,
	* coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c,
	* coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c,
	* coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c,
	* coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
	* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
	* coffcode.h, * coffgen.c, * cofflink.c, * compress.c,
	* corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c,
	* cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c,
	* cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c,
	* cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c,
	* cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c,
	* cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c,
	* cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c,
	* cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c,
	* cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c,
	* cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c,
	* cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c,
	* cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c,
	* cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c,
	* cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c,
	* cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c,
	* cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c,
	* cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c,
	* cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c,
	* cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c,
	* cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c,
	* cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c,
	* dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c,
	* elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h,
	* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c,
	* elf-nacl.h, * elf-properties.c, * elf-s390-common.c,
	* elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h,
	* elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c,
	* elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c,
	* elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c,
	* elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c,
	* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
	* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
	* elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c,
	* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
	* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
	* elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c,
	* elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
	* elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c,
	* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
	* elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c,
	* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
	* elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c,
	* elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h,
	* elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h,
	* elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c,
	* elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h,
	* elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
	* elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c,
	* elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c,
	* elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c,
	* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
	* elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c,
	* elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h,
	* elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c,
	* elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c,
	* elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h,
	* elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h,
	* elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h,
	* elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h,
	* format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c,
	* i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h,
	* libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h,
	* libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c,
	* mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h,
	* merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c,
	* pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c,
	* pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c,
	* pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c,
	* peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c,
	* reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c,
	* som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c,
	* verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h,
	* wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c,
	* xsym.h: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* libcoff.h: Regenerate.
 2021-03-31 10:49:23 +10:30
Alan Modra
1201fda61b hash table iterator callback functions int vs. bfd_boolean 
Correct return type of callbacks invoked by htab_traverse and other
hashtab.h functions to int, and one case of a callback invoked by
elf_link_hash_traverse to bfd_boolean.

	* elf32-i386.c (elf_i386_finish_local_dynamic_symbol): Return int.
	* elf64-ia64-vms.c (elf64_ia64_local_dyn_info_free): Likewise.
	(elf64_ia64_local_dyn_sym_thunk): Likewise.
	* elf64-x86-64.c (elf_x86_64_finish_local_dynamic_symbol): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_allocate_local_ifunc_dynrelocs),
	(elfNN_aarch64_finish_local_dynamic_symbol): Likewise.
	* elfnn-ia64.c (elfNN_ia64_local_dyn_info_free): Likewise.
	(elfNN_ia64_local_dyn_sym_thunk): Likewise.
	* elfnn-riscv.c (allocate_local_ifunc_dynrelocs): Likewise.
	(riscv_pcrel_reloc_eq): Likewise.
	(riscv_elf_finish_local_dynamic_symbol): Likewise.
	* elfxx-sparc.c (allocate_local_dynrelocs): Likewise.
	(finish_local_dynamic_symbol): Likewise.
	* elfxx-x86.c (elf_x86_allocate_local_dynreloc): Likewise.
	* elfxx-mips.c (mips_elf_resolve_got_page_ref): Likewise.
	(mips_elf_count_got_symbols): Change return type to bfd_boolean.
 2021-03-29 11:22:21 +10:30
Alan Modra
0f68420117 elf_backend_relocate_section int vs. bfd_boolean 
This functions was changed to return an int in commit ece5ef6079 but
since bfd_boolean was an int typedef I lazily left all the ELF
relocate_section functions as returning bfd_boolean, except the SPU
one.  In order to use _Bool or bool in place of bfd_boolean we need to
be fussy about the return types.

	* elf-m10200.c (mn10200_elf_relocate_section): Return int.
	* elf-m10300.c (mn10300_elf_relocate_section): Likewise.
	* elf32-arc.c (elf_arc_relocate_section): Likewise.
	* elf32-arm.c (elf32_arm_relocate_section): Likewise.
	* elf32-avr.c (elf32_avr_relocate_section): Likewise.
	* elf32-bfin.c (bfin_relocate_section): Likewise.
	(bfinfdpic_relocate_section): Likewise.
	* elf32-cr16.c (elf32_cr16_relocate_section): Likewise.
	* elf32-cris.c (cris_elf_relocate_section): Likewise.
	* elf32-crx.c (elf32_crx_relocate_section): Likewise.
	* elf32-csky.c (csky_elf_relocate_section): Likewise.
	* elf32-d10v.c (elf32_d10v_relocate_section): Likewise.
	* elf32-epiphany.c (epiphany_elf_relocate_section): Likewise.
	* elf32-fr30.c (fr30_elf_relocate_section): Likewise.
	* elf32-frv.c (elf32_frv_relocate_section): Likewise.
	* elf32-ft32.c (ft32_elf_relocate_section): Likewise.
	* elf32-h8300.c (elf32_h8_relocate_section): Likewise.
	* elf32-hppa.c (elf32_hppa_relocate_section): Likewise.
	* elf32-i386.c (elf_i386_relocate_section): Likewise.
	* elf32-ip2k.c (ip2k_elf_relocate_section): Likewise.
	* elf32-iq2000.c (iq2000_elf_relocate_section): Likewise.
	* elf32-lm32.c (lm32_elf_relocate_section): Likewise.
	* elf32-m32c.c (m32c_elf_relocate_section): Likewise.
	* elf32-m32r.c (m32r_elf_relocate_section): Likewise.
	* elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Likewise.
	* elf32-m68hc1x.h (elf32_m68hc11_relocate_section): Likewise.
	* elf32-m68k.c (elf_m68k_relocate_section): Likewise.
	* elf32-mcore.c (mcore_elf_relocate_section): Likewise.
	* elf32-mep.c (mep_elf_relocate_section): Likewise.
	* elf32-metag.c (elf_metag_relocate_section): Likewise.
	* elf32-microblaze.c (microblaze_elf_relocate_section): Likewise.
	* elf32-moxie.c (moxie_elf_relocate_section): Likewise.
	* elf32-msp430.c (elf32_msp430_relocate_section): Likewise.
	* elf32-mt.c (mt_elf_relocate_section): Likewise.
	* elf32-nds32.c (nds32_elf_relocate_section): Likewise.
	* elf32-nios2.c (nios2_elf32_relocate_section): Likewise.
	* elf32-or1k.c (or1k_elf_relocate_section): Likewise.
	* elf32-ppc.c (ppc_elf_relocate_section): Likewise.
	* elf32-pru.c (pru_elf32_relocate_section): Likewise.
	* elf32-rl78.c (rl78_elf_relocate_section): Likewise.
	* elf32-rx.c (rx_elf_relocate_section): Likewise.
	* elf32-s390.c (elf_s390_relocate_section): Likewise.
	* elf32-score.c (s3_bfd_score_elf_relocate_section): Likewise.
	(_bfd_score_elf_relocate_section): Likewise.
	* elf32-score.h (s7_bfd_score_elf_relocate_section): Likewise.
	* elf32-score7.c (s7_bfd_score_elf_relocate_section): Likewise.
	* elf32-sh.c (sh_elf_relocate_section): Likewise.
	* elf32-tic6x.c (elf32_tic6x_relocate_section): Likewise.
	* elf32-tilepro.c (tilepro_elf_relocate_section): Likewise.
	* elf32-v850.c (v850_elf_relocate_section): Likewise.
	* elf32-vax.c (elf_vax_relocate_section): Likewise.
	* elf32-visium.c (visium_elf_relocate_section): Likewise.
	* elf32-xc16x.c (elf32_xc16x_relocate_section): Likewise.
	* elf32-xstormy16.c (xstormy16_elf_relocate_section): Likewise.
	* elf32-xtensa.c (elf_xtensa_relocate_section): Likewise.
	* elf32-z80.c (z80_elf_relocate_section): Likewise.
	* elf64-alpha.c (elf64_alpha_relocate_section_r): Likewise.
	(elf64_alpha_relocate_section): Likewise.
	* elf64-bpf.c (bpf_elf_relocate_section): Likewise.
	* elf64-hppa.c (elf64_hppa_relocate_section): Likewise.
	* elf64-ia64-vms.c (elf64_ia64_relocate_section): Likewise.
	* elf64-mmix.c (mmix_elf_relocate_section): Likewise.
	* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
	* elf64-s390.c (elf_s390_relocate_section): Likewise.
	* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_relocate_section): Likewise.
	* elfnn-ia64.c (elfNN_ia64_relocate_section): Likewise.
	* elfnn-riscv.c (riscv_elf_relocate_section): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_relocate_section): Likewise.
	* elfxx-mips.h (_bfd_mips_elf_relocate_section): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Likewise.
	* elfxx-sparc.h (_bfd_sparc_elf_relocate_section): Likewise.
	* elfxx-tilegx.c (tilegx_elf_relocate_section): Likewise.
	* elfxx-tilegx.h (tilegx_elf_relocate_section): Likewise.
 2021-03-29 11:22:21 +10:30
Nelson Chu
ebdcad3fdd RISC-V: Improve multiple relax passes problem. 
According to the commit abd20cb637, an
intersting thing is that - the more relax passes, the more chances of
relaxations are reduced [1].  Originally, we set the boolean `again`
to TRUE once the code is actually deleted, and then we run the relaxations
repeatedly if `again` is still TRUE.  But `again` only works for the
relax pass itself, and won't affect others.  That is - we can not use
`again` to re-run the relax pass when we already enter into the following
passes (can not run the relax passes backwards).  Besides, we must seperate
the PCREL relaxations into two relax passes for some reasons [2], it make
us lose some relax opportunities.

This patch try to fix the problem, and the basic idea was come from Jim
Wilson - we use a new boolean, restart_relax, to determine if we need to
run the whole relax passes again from 0 to 2.  Once we have deleted the
code between relax pass 0 to 2, the restart_relax will be set to TRUE,
we should run the whole relaxations again to give them more chances to
shorten the code.  We will only enter into the relax pass 3 when the
restart_relax is FALSE, since we can't relax anything else once we start
to handle the alignments.

I have passed the gcc/binutils regressions by riscv-gnu-toolchain, and
looks fine for now.

[1] https://sourceware.org/pipermail/binutils/2020-November/114223.html
[2] https://sourceware.org/pipermail/binutils/2020-November/114235.html

bfd/
    * elfnn-riscv.c (riscv_elf_link_hash_table): New boolean restart_relax,
    used to check if we need to run the whole relaxations from relax pass 0
    to 2 again.
    (riscv_elf_link_hash_table_create): Init restart_relax to FALSE.
    (_bfd_riscv_relax_align): Remove obsolete sec_flg0 set.
    (_bfd_riscv_relax_delete): Set again to TRUE if we do delete the code.
    (bfd_elfNN_riscv_restart_relax_sections): New function.  Called by
    after_allocation to check if we need to run the whole relaxations again.
    (_bfd_riscv_relax_section): We will only enter into the relax pass 3 when
    the restart_relax is FALSE; At last set restart_relax to TRUE if again is
    TRUE, too.
    * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Declaration.
    (bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
    * emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments many
    times if riscv_restart_relax_sections returns TRUE.
    * testsuite/ld-riscv-elf/restart-relax.d: New testcase.  Before applying
    this patch, the call won't be relaxed to jal; But now we have more chances
    to do relaxations.
    * testsuite/ld-riscv-elf/restart-relax.s: Likewise.
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2021-03-11 17:27:13 +08:00
Andrew Burgess
0897bb7d6d bfd/riscv: prepare to handle bare metal core dump creation 
When creating a core file GDB will call the function
elfcore_write_prstatus to write out the general purpose registers
along with the pid/tid for the thread (into a prstatus structure) and
the executable name and arguments (into a prpsinfo_t structure).

However, for a bare metal RISC-V tool chain the prstatus_t and
prpsinfo_t types are not defined so the elfcore_write_prstatus
function will return NULL, preventing core file creation.

This commit provides the `elf_backend_write_core_note' hook and uses
the provided function to write out the required information.

In order to keep changes in the non bare metal tools to a minimum, the
provided backend function will itself return NULL when the prstatus_t
or pspsinfo_t types are available, the consequence of this is that the
generic code in elfcore_write_prstatus will be used just as before.
But, when prstatus_t or prpsinfo_t is not available, the new backend
function will write out the information using predefined offsets.

This new functionality will be used by a later GDB commit that will
add bare metal core dumps for RISC-V.

bfd/ChangeLog:

	* elfnn-riscv.c (PRPSINFO_PR_FNAME_LENGTH): Define.
	(PRPSINFO_PR_PSARGS_LENGTH): Define.
	(riscv_write_core_note): New function.
	(riscv_elf_grok_psinfo): Make use of two new length defines.
	(elf_backend_write_core_note): Define.
 2021-03-05 17:21:41 +00:00
Nelson Chu
5a9f5403c7 RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,

[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM:            Renamed from SBTYPE_IMM.
JTYPE_IMM:            Renamed from UJTYPE_IMM.
CITYPE_IMM:           Renamed from RVC_IMM.
CITYPE_LUI_IMM:       Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM:  Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM:      Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM:      Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM:          Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM:          Added for .insn without special encoding.
CSSTYPE_SWSP_IMM:     Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM:     Renamed from RVC_SDSP_IMM.
CLTYPE_IMM:           Added for .insn without special encoding.
CLTYPE_LW_IMM:        Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM:        Renamed from RVC_LD_IMM.
RVC_SIMM3:            Unused and removed.
CBTYPE_IMM:           Renamed from RVC_B_IMM.
CJTYPE_IMM:           Renamed from RVC_J_IMM.

* Added new operands and removed the unused ones,

C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.

bfd/
    PR 27158
    * elfnn-riscv.c (perform_relocation): Updated encoding macros.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    * elfxx-riscv.c (howto_table): Likewise.
gas/
    PR 27158
    * config/tc-riscv.c (riscv_ip): Updated encoding macros.
    (md_apply_fix): Likewise.
    (md_convert_frag_branch): Likewise.
    (validate_riscv_insn): Likewise.  Also arranged operands, including
    added C5 and C6 operands, and removed unused Ci and C< operands.
    * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
    * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
    * testsuite/gas/riscv/insn.s: Likewise.
gdb/
    PR 27158
    * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
    (decode_j_type_insn): Likewise.
    (decode_cj_type_insn): Likewise.
    (decode_b_type_insn): Likewise.
    (decode): Likewise.
include/
    PR 27158
    * opcode/riscv.h: Updated encoding macros.
opcodes/
    PR 27158
    * riscv-dis.c (print_insn_args): Updated encoding macros.
    * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
    (match_c_addi16sp): Updated encoding macros.
    (match_c_lui): Likewise.
    (match_c_lui_with_hint): Likewise.
    (match_c_addi4spn): Likewise.
    (match_c_slli): Likewise.
    (match_slli_as_c_slli): Likewise.
    (match_c_slli64): Likewise.
    (match_srxi_as_c_srxi): Likewise.
    (riscv_insn_types): Added .insn css/cl/cs.
sim/
    PR 27158
    * riscv/sim-main.c (execute_i): Updated encoding macros.
 2021-02-19 11:44:49 +08:00
Nelson Chu
3d73d29e4e RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. 
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h.  Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use.  To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros.  Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.

bfd/
    * Makefile.am: Added cpu-riscv.h.
    * Makefile.in: Regenerated.
    * po/SRC-POTFILES.in: Regenerated.
    * cpu-riscv.h: Added to support spec versions controlling.
    Also added extern arrays and functions for cpu-riscv.c.
    (enum riscv_spec_class): Define all spec classes here uniformly.
    (struct riscv_spec): Added for all specs.
    (RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
    (RISCV_GET_SPEC_NAME): Likewise.
    (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
    (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
    (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
    * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
    (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
    (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
    (riscv_priv_specs): Moved below.
    (riscv_get_priv_spec_class_from_numbers): Likewise, updated.
    (riscv_isa_specs): Moved from include/opcode/riscv.h.
    * elfnn-riscv.c: Included cpu-riscv.h.
    (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
    * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
    (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
    * elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
    * config/tc-riscv.c: Included cpu-riscv.h.
    (enum riscv_csr_clas): Moved from include/opcode/riscv.h.
    (struct riscv_csr_extra): Likewise.
    (struct riscv_ext_version): Likewise.
    (ext_version_table): Moved from opcodes/riscv-opc.c.
    (default_isa_spec): Updated type to riscv_spec_class.
    (default_priv_spec): Likewise.
    (riscv_set_default_isa_spec): Updated.
    (init_ext_version_hash): Likewise.
    (riscv_init_csr_hash): Likewise, also fixed indent.
include/
    * opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
    * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
    (default_priv_spec): Updated type to riscv_spec_class.
    (parse_riscv_dis_option): Updated.
    * riscv-opc.c: Moved stuff and make the file tidy.
 2021-02-18 15:09:16 +08:00
Nelson Chu
0d6aab7776 RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one. 
RISC-V only defines two float ABIs, soft-float and double-float, and the
value of soft-float is 0x0.  But 0x0 usually means unknown/default setting
for many targets, and the non-ABI binary, which is generated by "ld/objcopy
-b binary", also has the 0x0 elf header flags, this may be confused.

We probably can define a new unknown/default ABI value to make them more
clear, but that will need more bits in the elf header flags, and also need
to discuss in the riscv psabi spec.

Training linker have a default ABI setting, and can be changed by ld
options or configure options is another solution, like what assemblr
usually do.  So all objects, including the binary files, will have
explicit ABI setting.  But the binary files will no longer be linked
with any object, users need to recompile them with the exactly ABI
they want.  It may be inconvenience sometimes.  Besides, I think linker
doesn't need to know the default arch/abi so far, just set them according
to the linked objects should be enough.

Therefore, without changing the riscv psabi, and keep the non-ABI binary
can be linked with any object, we don't check the ABI flags if no code
section in the PR24389.  Just that we find the first input non-ABI binary
still cannot be linked with others in the PR27200.  This patch fixs the
problem by delaying the elf_flags_init(obfd) check, since the flags of
non-ABI object with no code cannot be copyed to output BFD, we should
skip it, even if it is the first linked object.

However, there is a strange "break" at the end of loop in the PR24389.
The "break" cause the ld testcase "Link with zlib-gabi compressed debug
output 1" fails for rv64gc-linux toolchain, after applying the above
change.  The root cause is that - the "break" make linker only checks
the "first" section of input BFD rather than the entire sections.
I have checked that AARCH64 and ARM both have the "break" at the end
of loop, but ARC doesn't.  I suppose we should remove the "break" like
what ARC do, or use a pair of braces for the if statement.

I have passed the elf/linux toolchain regressions, so the change should
be fine.

bfd/
    PR 27200
    * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Delay
    copying the elf flags from input BFD to output BFD, until we have
    checked if the input BFD has no code section or not.  Also fix the
    problem that we only check the first section rather than the entire
    sections for input BFD.
 2021-02-17 11:02:09 +08:00
Nelson Chu
4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits accidentally. 
bfd/
    * elfnn-riscv.c (riscv_relax_delete_bytes): Fixed the indent that
    caused by the previous commit accidentally.
 2021-01-15 18:13:30 +08:00
Nelson Chu
1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned the code. 
bfd/
    * elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
    also aligned the code.
gas/
    * config/tc-riscv.c: Indent and GNU coding standards tidy,
    also aligned the code.
    * config/tc-riscv.h: Likewise.
include/
    * opcode/riscv.h: Indent and GNU coding standards tidy,
    also aligned the code.
opcodes/
    * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
    (riscv_fpr_names_abi): Likewise.
    (riscv_opcodes): Likewise.
    (riscv_insn_types): Likewise.
 2021-01-15 17:41:18 +08:00
Nelson Chu
b800637e76 RISC-V: Error and warning messages tidy. 
Error and warning messages usually starting with lower case letter,
and without the period at the end.  Besides, add the prefixed "internel:"
at the beginning of the messages when they are caused internally.
Also fix indents and typos.

bfd/
    * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages.
gas/
    * config/tc-riscv.c: Error and warning messages tidy.
    * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated.
    * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
ld/
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
opcodes/
    * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 2021-01-15 17:33:59 +08:00
Nelson Chu
dcd709e056 RISC-V: Comments tidy and improvement. 
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces.  But sometimes it should be more
cleaner when the comments only include a word or codes.  Therefore, I made
the following changes after referring to other target/generic codes,

* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.

Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.

bfd/
    * elfnn-riscv.c: Comments tidy and improvement.
    * elfxx-riscv.c: Likewise.
    * elfxx-riscv.h: Likewise.
gas/
    * config/tc-riscv.c: Comments tidy and improvement.  Also update
    comment "fallthru" to "Fall through" that end with a period and
    two spaces.
include/
    * elf/riscv.h: Comments tidy and improvement.
    * opcode/riscv-opc.h: Likewise.
    * opcode/riscv.h: Likewise.
opcodes/
    * riscv-dis.c: Comments tidy and improvement.
    * riscv-opc.c: Likewise.
 2021-01-15 17:28:07 +08:00
Marcus Comstedt
fbc09e7af7 RISC-V: Implement support for big endian targets. 
RISC-V instruction/code is always little endian, but data might be
big-endian.  Therefore, we can not use the original bfd_get/bfd_put
to get/put the code for big endian targets.  Add new riscv_get_insn
and riscv_put_insn to always get/put code as little endian can resolve
the problem.  Just remember to update them once we have supported
the 48-bit/128-bit instructions in the future patches.

bfd/
    * config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and
    riscvbe*-*-*.  Also added riscv_elf[32|64]_be_vec.
    * configure.ac: Handle riscv_elf[32|64]_be_vec.
    * configure: Regenerate.
    * elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for
    riscv_is_insn_reloc.
    (riscv_get_insn): RISC-V instructions are always little endian, but
    bfd_get may be used for big-endian, so add new riscv_get_insn to handle
    the insturctions.
    (riscv_put_insn): Likewsie.
    (riscv_is_insn_reloc): Check if we are relocaing an instruction.
    (perform_relocation): Call riscv_is_insn_reloc to decide if we should
    use riscv_[get|put]_insn or bfd_[get|put].
    (riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32
    or bfd_[get|put]l16 for code.
    (riscv_elf_relocate_section): Likewise.
    (riscv_elf_finish_dynamic_symbol): Likewise.
    (riscv_elf_finish_dynamic_sections): Likewise.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    (_bfd_riscv_relax_align): Likewise.
    (_bfd_riscv_relax_pc): Likewise.
    (riscv_elf_object_p): Handled for big endian.
    (TARGET_BIG_SYM, TARGET_BIG_NAME): Defined.
    * targets.c: Add riscv_elf[32|64]_be_vec.
    (_bfd_target_vector): Likewise.

gas/
    * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
    elf32-bigriscv.
    (install_insn): Always write instructions as little endian.
    (riscv_make_nops): Likewise.
    (md_convert_frag_branch): Likewise.
    (md_number_to_chars): Write data in target endianness.
    (options, md_longopts): Add -mbig-endian and -mlittle-endian options.
    (md_parse_option): Handle the endian options.
    * config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
    already defined.
    * configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.

ld/
    * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
    riscv32be*-*-linux*, and riscv64be*-*-linux*.
    * Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and
    eelf32briscv_ilp32.c.
    * Makefile.in: Regenerate.
    * emulparams/elf32briscv.sh: Added.
    * emulparams/elf32briscv_ilp32.sh: Likewise.
    * emulparams/elf32briscv_ilp32f.sh: Likewise.
    * emulparams/elf64briscv.sh: Likewise.
    * emulparams/elf64briscv_lp64.sh: Likewise.
    * emulparams/elf64briscv_lp64f.sh: Likewise.
 2021-01-06 17:57:52 +08:00
Nelson Chu
18b9872261 RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE. 
When the ifunc resolver is in the executable, we may relax the variables
to gp-relative access instruction in the ifunc resolver, or in other functions
that called by the ifunc resolver.  But this will cause the uninitialized
gp problem since the ifunc need to be resolved at the early runtime, that
is at the pre-load stage, but we set the gp until the startup code.

At first, we try to add a new dynamic tag, DT_RISCV_GP, to stroe the gp value
and let ld.so can init the gp register early, before the pre-load stage.  But
we need to extend the ABI if we want to add a new dynamic tag.  Therefore,
in the psabi discussion, we try another solution, which was suggested by the
lld and FreeBSD linker experts, to let ld.so set the gp earlier - make sure
__global_pointer$ is output as a dynamic symbol when we are generating pde,
since we only do the relaxation for it.  Afterwards, ld.so can search the
DT_SYMTAB to get the gp value, and set the gp register before resolving ifunc.

bfd/
    * elfnn-riscv.c (allocate_dynrelocs): When we are generating pde, make
      sure gp symbol is output as a dynamic symbol.
 2021-01-05 10:18:33 +08:00
Nelson Chu
4c0e540e47 RISC-V: Fix the merged orders of Z* extension for linker. 
Similar to the commit 6729e2c2af,
we have to check the first char of the Z* extensions, to make
sure that they follow the order of the standard extensions.

bfd/
    * elfxx-riscv.c (riscv_compare_subsets): Removed static.
    * elfxx-riscv.h: Add declaration.
    * elfnn-riscv.c (riscv_merge_multi_letter_ext): Use
    riscv_compare_subsets to check the orders.
    (riscv_skip_prefix): Removed.
    (riscv_prefix_cmp): Removed.
 2021-01-04 11:17:33 +08:00
Alan Modra
250d07de5c Update year range in copyright notice of binutils files 2021-01-01 10:31:05 +10:30
Nelson Chu
dfe9249667 RISC-V: Support to add implicit extensions. 
We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions.  That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions.  For now we
follow the following rules to add the implicit extensions,

* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.

Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.

	bfd/
	* elfnn-riscv.c (riscv_merge_std_ext): Updated since
	riscv_lookup_subset is changed.
	* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
	extensions' order quickly.
	(riscv_init_ext_order): New function.  Init the riscv_ext_order
	according to the riscv_supported_std_ext and parse_config[i].class
	automatically.
	(riscv_compare_subsets): New function.  Similar to the strcmp, but
	compare the subsets with the specific order.
	(riscv_lookup_subset): Return TRUE and set `current` to the subset
	if it is found.  Otherwise, return FALSE and set `current` to the
	place where we should insert the subset.
	(riscv_add_implicit_subset): New function.  Search the list first,
	and then find the right place to add the implicit_subset.
	(riscv_parse_add_subset): Since We have to add all arch string
	extensions first, and then start to add their implicit extensions.
	We can add arch string extensions in order by the original
	riscv_add_subset, and then add the implicit subsets by the
	riscv_add_implicit_subset.  Besides, do not add the implicit
	extensions if we failed to find their default versions.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_add_implicit_subsets): New function.  Add all implicit
	extensions according to the arch string extensions.
	(riscv_parse_subset): Call riscv_init_ext_order and
	riscv_parse_add_implicit_subsets, before and after parsing the
	arch string.  Remove parts of the ISA conflict checking since
	the implicit extensions are added.
	* elfxx-riscv.h (riscv_lookup_subset): Updated.

	gas/
	* config/tc-riscv.c (riscv_subset_supports): Updated.
	* testsuite/gas/riscv/march-imply-i2p0.d: New testcase.  Need to
	add the implicit zicsr and zifencei when i's version less than 2.1.
	* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
	* testsuite/gas/riscv/march-imply-d.d: Likewise.
	* testsuite/gas/riscv/march-imply-f.d: Likewise.
	* testsuite/gas/riscv/march-imply-q.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
	* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
 2020-12-01 15:18:48 +08:00
Nelson Chu
abd20cb637 RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous. 
I get the feedback recently that enable linker relaxations may fail to
build some program.  Consider the following case,

	.text
foo:
	addi	a0, a0, %pcrel_lo(.L2)
	call	foo
.L1:	auipc	a1, %pcrel_hi(data_g)
	addi	a1, a1, %pcrel_lo(.L1)
	lui	a2, %hi(data_g)
	addi	a2, a2, %lo(data_g)
	lui	a3, %tprel_hi(data_t)
	add	a3, a3, tp, %tprel_add(data_t)
	addi	a3, a3, %tprel_lo(data_t)
.L2:	auipc	a0, %pcrel_hi(data_g)

	.data
	.word 0x0
	.global data_g
data_g:	.word 0x1

	.section .tbss
data_t:	.word 0x0

The current ld reports `dangerous relocation error` when doing the
pcgp relaxation,
test.o: in function `foo':
(.text+0x0): dangerous relocation: %pcrel_lo missing matching %pcrel_hi

The .L2 auipc should not be removed since it is behind the corresponding
addi, so we record the information in the pcgp_relocs table to avoid
removing the auipc later.  But current ld still remove it since we do not
update the pcgp_relocs table while doing other relaxations.  I have two
solutions to fix the problem,

1. Update the pcgp_relocs table once we actually delete the code.
2. Add new relax pass to do the pcgp relaxations

At first I tried to do the first solution, and we need to update at
least three information - hi_sec_off of riscv_pcgp_lo_reloc, hi_sec_off
and hi_addr (symbol value) of riscv_pcgp_hi_reloc.  Update the hi_sec_off
is simple, but it is more complicate to update the symbol value, since we
almost have to do parts the same works of _bfd_riscv_relax_call again in
the riscv_relax_delete_bytes to get the correct symbol value.

Compared with the first solution, the second one is more intuitive and
simple.  We add a new relax pass to do the pcgp relaxations later, so
we will get all the information correctly in the _bfd_riscv_relax_call,
including the symbol value, without changing so much code.  I do not see
any penalty by adding a new relax pass for now, so it should be fine
to delay the pcgp relaxations.

Besides, I have pass all riscv-gnu-toolchain regressions for this patch.

	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_section):  Add a new relax pass
	to do the pcgp relaxation later, after the lui and call relaxations,
	but before the delete and alignment relaxations.

	ld/
	* emultempl/riscvelf.em (riscv_elf_before_allocation): Change
	link_info.relax_pass from 3 to 4.
	* testsuite/ld-riscv-elf/pcgp-relax.d: New testcase.
	* testsuite/ld-riscv-elf/pcgp-relax.s: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2020-11-21 09:41:58 +08:00
Nelson Chu
51a8a7c2e3 RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place. 
For the ifunc symbol, which is referenced by GOT rather than PLT relocs,
we should add the dynamic reloc (usually IRELATIVE) into the .rel.iplt
when generating the static executable.  But if we use riscv_elf_append_rela
to add the dynamic relocs into .rela.iplt, this may cause the overwrite
problem.

The reason is that we don't handle the `reloc_index` of .rela.iplt, but
the riscv_elf_append_rela adds the relocs to the place that are calculated
from the reloc_index (in seqential).  Therefore, we may overwrite the
dynamic relocs when the `reloc_index` of .rela.iplt isn't handled correctly.

One solution is that we can add these dynamic relocs (GOT ifunc) from
the last of .rela.iplt section.  But I'm not sure if it is the best way.

	bfd/
	* elfnn-riscv.c (riscv_elf_link_hash_table): Add last_iplt_index.
	(riscv_elf_size_dynamic_sections): Initialize the last_iplt_index.
	(riscv_elf_relocate_section): Use riscv_elf_append_rela.
	(riscv_elf_finish_dynamic_symbol): If the use_elf_append_rela is
	false, then we should add the dynamic relocs from the last of
	the .rela.iplt, and don't use the riscv_elf_append_rela to add.

	ld/
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2020-10-16 10:11:23 +08:00
Nelson Chu
02dd9d2568 RISC-V: Support GNU indirect functions. 
Generally, glibc dynamic linker should have two ways to deal with ifunc
- one is to handle the IRELATIVE relocations for the non-preemtive ifunc
symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT
relocations with the STT_IFUNC preemtive symbols.  No matter which method
is used, both of them should get the resolved ifunc symbols at runtime.
Therefore, linker needs to generate the correct dynamic relocations for
ifunc to make sure the the dynamic linker works well.  For now, there are
thirteen relocations are supported for ifunc in GNU ld,

* R_RISCV_CALL and R_RISCV_CALL_PLT:
The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an
ifunc.  Besides, we disable the relaxations for the relocation referenced
to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be
enough.  Linker should generate a .plt entry and a .got.plt entry for it,
and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or
insert a R_RISCV_JUMP_SLOT when generating shared library.

* R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S:
LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol.
The PC-relative relocation.  The current linker will deal with them in
the same way as R_RISCV_CALL_PLT.

* R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S:
LA pattern with global PIC ifunc symbol.  Linker should insert a dynamic
IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating
shared library.

* R_RISCV_32 and R_RISCV_64:
Store the ifunc symbol into the data section.  Linker should insert a
dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when
generating shared library.

* R_RISCV_HI20 and R_RISCV_LO12_I/S:
The LUI + ADDI/LW/SW patterns.  The absolute access relocation.  The
medlow model without the -fPIC compiler option should generate them.
The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the
relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler
support.

However, we also made some optimizations with reference to x86,

* If GOT and PLT relocations refer to the same ifunc symbol when generating
pie, then they can actually share a .got entry without creating two entries
to store the same value and relocation.

* If GOT, PLT and DATA relocations refer to the same ifunc symbol when
generating position dependency executable, then linker will fill the address
of .plt entry into the corresponding .got entry and data section, without
insert any dynamic relocations for the GOT and DATA relocations.

For the ifunc testcases, there are three types of them,

1. ifunc-reloc-*: Only check the single type of relocation refers to
ifunc symbol.
* ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT.
* ifunc-reloc-data: R_RISCV_32 and R_RISCV_64.
* ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S.
* ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S.

2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to
create the PLT and it's .plt entries.
* ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64.
* ifunc-plt: Combine all ifunc relocations.

3. ifunc-seperate-*: If we link the ifunc caller and resolver into the
same module (link the objects), then the results are the same as the
ifunc-reloc-* and ifunc-[noplt|plt]-* testcases.  Consider the cases that
the ifunc callers and resolver are in the different modules, that is, we
compile the ifunc resolver to the shared library first, and then link it
with the ifunc callers.  The output of ifunc callers should be the same as
the normal STT_FUNC cases, and the shared ifunc resolver should define the
symbols as STT_IFUNC.

The R_RISCV_PCREL_HI20 reloc is special.  It should be linked and resolved
locally, so if the ifunc resolver is defined in other modules (other shared
libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should
issue an unresolvable reloc error.

	bfd/
	* elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc.
	(riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory
	for local STT_GNU_IFUNC symbols.
	(riscv_elf_got_plt_val): Removed.
	(riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions.
	Use to compare local hash entries.
	(riscv_elf_get_local_sym_hash): New function.  Find a hash entry for
	local symbol, and create a new one if needed.
	(riscv_elf_link_hash_table_free): New function.  Destroy an riscv
	elf linker hash table.
	(riscv_elf_link_hash_table_create): Create hash table for local ifunc.
	(riscv_elf_check_relocs): Create a fake global symbol to track the
	local ifunc symbol.  Add support to check and handle the relocations
	reference to ifunc symbols.
	(allocate_dynrelocs): Let allocate_ifunc_dynrelocs and
	allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they
	are defined and referenced in a non-shared object.
	(allocate_ifunc_dynrelocs): New function.  Allocate space in .plt,
	.got and associated reloc sections for ifunc dynamic relocs.
	(allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc
	dynamic relocs.
	(riscv_elf_relocate_section): Add support to handle the relocation
	referenced to ifunc symbols.
	(riscv_elf_size_dynamic_sections): Updated.
	(riscv_elf_adjust_dynamic_symbol): Updated.
	(riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling,
	including fill the PLT and GOT entries for ifunc symbols.
	(riscv_elf_finish_local_dynamic_symbol): New function.  Called by
	riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols.
	(_bfd_riscv_relax_section): Don't do the relaxation for ifunc.
	* elfxx-riscv.c: Add R_RISCV_IRELATIVE.
	* configure.ac: Link elf-ifunc.lo to use the generic ifunc support.
	* configure: Regenerated.

	include/
	* elf/riscv.h: Add R_RISCV_IRELATIVE to 58.

	ld/
	* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
	* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
	New dump test for ifunc.  There are two arguments, 'target` and
	`output`.  The `target` is rv32 or rv64, and the `output` is used
	to choose which output you want to test (exe, pie or .so).
	* testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
 2020-10-16 10:11:18 +08:00
Nelson Chu
9184ef8a92 RISC-V: Minor cleanup and typos when merging elf attributes. 
bfd/
	* elfnn-riscv.c (riscv_i_or_e_p): Minor cleanup for warnings/errors.
	(riscv_merge_std_ext): Likewise.
	(riscv_merge_arch_attr_info): Likewise.
	(riscv_merge_attributes): Likewise and fix comment typos.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Remove
	the useless `warnings` keywords.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
 2020-09-03 11:12:02 +08:00
Nelson Chu
32f0ce4db9 RISC-V: Report warnings rather than errors for the mis-matched ISA versions. 
Same as the privileged spec attributes check - different ISA versions
should be compatible, unless there are some known conflicts.  Therefore,
we should allow to link objects with different ISA versions, and update
the output ISA versions once the corresponding input ones are newer.
But it's better to also warn people that the conflicts may happen when
the ISA versions are mis-matched.

	bfd/
	* elfnn-riscv.c (riscv_version_mismatch): Change the return type
	from void to bfd_boolean.  Report warnings rather than errors
	when the ISA versions are mis-matched.  Afterwards, remember to
	update the output ISA versions to the newest ones.
	(riscv_merge_std_ext): Allow to link objects with different
	standard ISA versions.  Try to add output ISA versions to
	merged_subsets first.
	(riscv_merge_multi_letter_ext): Likewise.  But for standard additional
	ISA and non-standard ISA versions.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update the
	message from error to warning.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: New testcases.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2020-09-03 11:11:51 +08:00
Kito Cheng
72bd6912ea RISC-V: Improve the error message for the mis-matched ISA versions. 
Consider the updated attr-merge-arch-failed-01.d testcase.  Extension
A's version are mis-matched between attr-merge-arch-failed-01a.s and
attr-merge-arch-failed-01b.s.  But the old binutils reports that the
mis-matched extension is M rather than A.  This commit is used to fix
the wrong mis-matched error message.

Besides, when parsing the arch string in the riscv_parse_subset, it
shouldn't be NULL or empty.  However, it might be empty when we failed
to merge the arch string in the riscv_merge_attributes.  Since we should
already issue the correct error message in another side, and the message
- ISA string must begin with rv32 or rv64 - is meaninglesss when the arch
string is empty, so do not issue it.

	bfd/
	* elfnn-riscv.c (riscv_merge_std_ext): Fix to report the correct
	error message when the versions of extension are mis-matched.
	* elfxx-riscv.c (riscv_parse_subset): Don't issue the error when
	the string is empty.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise.
 2020-09-03 11:11:38 +08:00
Alan Modra
1174d92070 PR26493 UBSAN: elfnn-riscv.c left shift of negative value 
include/
	PR 26493
	* opcode/riscv.h (OP_MASK_CSR, OP_MASK_CUSTOM_IMM)
	(OP_MASK_FUNCT7, OP_MASK_RS3): Make unsigned.
bfd/
	PR 26493
	* elfnn-riscv.c (riscv_make_plt_header): Cast PLT_HEADER_SIZE to
	unsigned when using with RISCV_ITYPE.
	(_bfd_riscv_relax_call): Use an unsigned foff.
 2020-08-31 20:28:10 +09:30
Nelson Chu
3b1450b38c RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs. 
In fact, we can treate these two relocation as the same one in the
riscv_elf_check_relocs.  I have heard that RISC-V lld had made this
improvement, and so had GNU AARCH64, they only need R_AARCH64_CALL26
for calls rather than two seperate relocations.

Beside, the following PLT issue for RISC-V 32-bit glibc seems to be
fixed by applying at least this patch.

<https://sourceware.org/pipermail/libc-alpha/2020-August/117214.html>

I have ran the toolchain regression, and everything seems fine for now.

	bfd/
	* elfnn-riscv.c (riscv_elf_check_relocs): Treat R_RISCV_CALL
	and R_RISCV_CALL_PLT as the same in the riscv_elf_check_relocs.
	(riscv_elf_relocate_section): Remove the R_RISCV_CALL for the
	unresolved reloc checks.

	ld/
	testsuite/ld-riscv-elf/lib-nopic-01a.s: Use R_RISCV_JAL rather
	than R_RISCV_CALL.
	testsuite/ld-riscv-elf/lib-nopic-01b.d: Likewise.
	testsuite/ld-riscv-elf/lib-nopic-01b.s: Likewise.
 2020-08-28 09:37:35 +08:00
Alan Modra
0f55320bc4 elf_hash_table_id access 
* elf-m10300.c (elf32_mn10300_hash_table): Test is_elf_hash_table
	before accessing elf_hash_table_id.
	* elf32-arc.c (elf_arc_hash_table): Likewise.
	* elf32-arm.c (elf32_arm_hash_table): Likewise.
	* elf32-avr.c (avr_link_hash_table): Likewise.
	* elf32-bfin.c (bfinfdpic_hash_table): Likewise.
	* elf32-cris.c (elf_cris_hash_table): Likewise.
	* elf32-csky.c (csky_elf_hash_table): Likewise.
	* elf32-frv.c (frvfdpic_hash_table): Likewise.
	* elf32-hppa.c (hppa_link_hash_table): Likewise.
	* elf32-lm32.c (lm32_elf_hash_table): Likewise.
	* elf32-m32r.c (m32r_elf_hash_table): Likewise.
	* elf32-m68hc1x.h (m68hc11_elf_hash_table): Likewise.
	* elf32-m68k.c (elf_m68k_hash_table): Likewise.
	* elf32-metag.c (metag_link_hash_table): Likewise.
	* elf32-microblaze.c (elf32_mb_hash_table): Likewise.
	* elf32-nds32.h (nds32_elf_hash_table): Likewise.
	* elf32-or1k.c (or1k_elf_hash_table): Likewise.
	* elf32-s390.c (elf_s390_hash_table): Likewise.
	* elf32-sh.c (sh_elf_hash_table): Likewise.
	* elf32-spu.c (spu_hash_table): Likewise.
	* elf32-tilepro.c (tilepro_elf_hash_table): Likewise.
	* elf32-xtensa.c (elf_xtensa_hash_table): Likewise.
	* elf64-alpha.c (alpha_elf_hash_table): Likewise.
	* elf64-hppa.c (hppa_link_hash_table): Likewise.
	* elf64-ia64-vms.c (elf64_ia64_hash_table): Likewise.
	* elf64-s390.c (elf_s390_hash_table): Likewise.
	* elfnn-ia64.c (elfNN_ia64_hash_table): Likewise.
	* elfnn-riscv.c (riscv_elf_hash_table): Likewise.
	* elfxx-mips.c (mips_elf_hash_table): Likewise.
	* elfxx-sparc.h (_bfd_sparc_elf_hash_table): Likewise.
	* elfxx-tilegx.c (tilegx_elf_hash_table): Likewise.
 2020-08-25 02:45:58 +09:30
H.J. Lu
f1dfbfdbc6 elf: Add sym_cache to elf_link_hash_table 
Since many ELF backends have sym_cache to their link hash tables, add
sym_cache to elf_link_hash_table.  Also use sdynbss and srelbss in
elf_link_hash_table.

	* elf-bfd.h (sym_cache): Moved before elf_link_hash_table.
	(elf_link_hash_table): Add sym_cache.
	* elf32-arm.c (elf32_arm_link_hash_table): Remove sym_cache.
	(elf32_arm_check_relocs): Updated.
	(elf32_arm_size_dynamic_sections): Likewise.
	* elf32-bfin.c (bfin_link_hash_table): Removed.
	(bfin_link_hash_newfunc): Updated.
	(bfin_hash_table): Removed.
	* elf32-csky.c (csky_elf_link_hash_table): Remove sym_cache.
	(csky_elf_check_relocs): Updated.
	* elf32-hppa.c (elf32_hppa_link_hash_table): Remove sym_cache.
	(elf32_hppa_check_relocs): Updated.
	* elf32-i386.c (elf_i386_tls_transition): Updated.
	(elf_i386_convert_load_reloc): Likewise.
	(elf_i386_check_relocs): Likewise.
	* elf32-m32r.c (elf_m32r_link_hash_table): Removed.
	(m32r_elf_hash_table): Updated.
	(m32r_elf_link_hash_table_create): Likewise.
	(m32r_elf_create_dynamic_sections): Likewise.
	(m32r_elf_adjust_dynamic_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	(m32r_elf_size_dynamic_sections): Likewise.
	(m32r_elf_relocate_section): Likewise.
	(m32r_elf_finish_dynamic_symbol): Likewise.
	(m32r_elf_check_relocs): Likewise.
	* elf32-m68hc1x.h (m68hc11_elf_link_hash_table): Remove
	sym_cache.
	* elf32-m68k.c (elf_m68k_link_hash_table): Likewise.
	(elf_m68k_check_relocs): Updated.
	* elf32-metag.c (elf_metag_link_hash_table): Remove sym_cache.
	(elf_metag_check_relocs): Updated.
	* elf32-microblaze.c (elf32_mb_link_hash_table): Remove sym_sec.
	(microblaze_elf_check_relocs): Updated.
	* elf32-nds32.c (nds32_elf_link_hash_table_create): Likewise.
	(nds32_elf_create_dynamic_sections): Likewise.
	(nds32_elf_adjust_dynamic_symbol): Likewise.
	(nds32_elf_check_relocs): Likewise.
	* elf32-nds32.h (elf_nds32_link_hash_table): Remove sdynbss,
	srelbss and aym_cache.
	* elf32-nios2.c (elf32_nios2_link_hash_table): Remove sym_cache.
	(nios2_elf32_check_relocs): Updated.
	* elf32-or1k.c (elf_or1k_link_hash_table): Remove sym_sec.
	(or1k_elf_check_relocs): Updated.
	* elf32-ppc.c (ppc_elf_check_relocs): Remove sym_cache.
	(ppc_elf_check_relocs): Updated.
	* elf32-s390.c (elf_s390_link_hash_table): Remove sym_cache.
	(elf_s390_check_relocs): Updated.
	(elf_s390_finish_dynamic_sections): Likewise.
	* elf32-sh.c (elf_sh_link_hash_table): Remove sdynbss, srelbss
	and aym_cache.
	(sh_elf_create_dynamic_sections): Updated.
	(sh_elf_adjust_dynamic_symbol): Likewise.
	(sh_elf_size_dynamic_sections): Likewise.
	(sh_elf_check_relocs): Likewise.
	* elf32-tic6x.c (elf32_tic6x_link_hash_table): Remove sym_cache.
	(elf32_tic6x_check_relocs): Updated.
	* elf32-tilepro.c (tilepro_elf_link_hash_table): Removed.
	(tilepro_elf_hash_table): Updated.
	(tilepro_elf_link_hash_table_create): Likewise.
	(tilepro_elf_check_relocs): Likewise.
	(tilepro_elf_adjust_dynamic_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	(tilepro_elf_size_dynamic_sections): Likewise.
	(tilepro_elf_relocate_section): Likewise.
	(tilepro_elf_finish_dynamic_symbol): Likewise.
	(tilepro_finish_dyn): Likewise.
	(tilepro_elf_finish_dynamic_sections): Likewise.
	* elf64-ppc.c (ppc_link_hash_table): Remove sym_cache.
	(ppc64_elf_before_check_relocs): Updated.
	(ppc64_elf_check_relocs): Likewise.
	* elf64-s390.c (elf_s390_link_hash_table): Remove sym_cache.
	(elf_s390_check_relocs): Updated.
	(elf_s390_relocate_section): Likewise.
	(elf_s390_finish_dynamic_sections): Likewise.
	* elf64-x86-64.c (elf_x86_64_tls_transition): Likewise.
	(elf_x86_64_check_relocs): Likewise.
	* elfnn-aarch64.c (elf_aarch64_link_hash_table): Remove
	sym_cache.
	(elfNN_aarch64_check_relocs): Updated.
	* elfnn-riscv.c (riscv_elf_link_hash_table): Remove sym_cache.
	(riscv_elf_check_relocs): Updated.
	* elfxx-mips.c (mips_elf_link_hash_table): Remove sym_cache.
	(mips_elf_resolve_got_page_ref): Updated.
	* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
	* elfxx-sparc.h (_bfd_sparc_elf_link_hash_table): Remove
	sym_cache.
	* elfxx-tilegx.c (tilegx_elf_link_hash_table): Likewise.
	(tilegx_elf_check_relocs): Updated.
	* elfxx-x86.h (elf_x86_link_hash_table): Remove sym_cache.
 2020-07-30 03:41:44 -07:00
H.J. Lu
3084d7a27b ELF: Add _bfd_elf_add_dynamic_tags 
All ELF backends with shared library support need to add dynamic tags.
Add dt_pltgot_required and dt_jmprel_required to elf_link_hash_table to
indicate that DT_PLTGOT and DT_JMPREL are required dynamic tags.

1. Add _bfd_elf_add_dynamic_tags to add common dynamic tags.
2. Add _bfd_elf_maybe_vxworks_add_dynamic_tags to add common VxWorks
dynamic tags.

	* elf-bfd.h (elf_link_hash_table): Add dt_pltgot_required and
	dt_jmprel_required.
	(_bfd_elf_add_dynamic_tags): New.
	* elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Call
	_bfd_elf_add_dynamic_tags.
	* elf32-arc.c (elf_arc_size_dynamic_sections): Likewise.
	* elf32-bfin.c (elf32_bfinfdpic_size_dynamic_sections): Likewise.
	* elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise.
	* elf32-frv.c (elf32_frvfdpic_size_dynamic_sections): Likewise.
	* elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise.
	* elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise.
	* elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise.
	* elf32-microblaze.c (microblaze_elf_size_dynamic_sections):
	Likewise.
	* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
	* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise.
	* elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise.
	* elf32-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
	* elf32-vax.c (elf_vax_size_dynamic_sections): Likewise.
	* elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections):
	Likewise.
	* elfnn-riscv.c (riscv_elf_size_dynamic_sections): Likewise.
	* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
	* elf32-arm.c (elf32_arm_size_dynamic_sections): Call
	_bfd_elf_maybe_vxworks_add_dynamic_tags.
	* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections):
	Likewise.
	* elfxx-x86.c (_bfd_x86_elf_link_hash_table_create): Likewise.
	(_bfd_x86_elf_size_dynamic_sections): Likewise.
	* elfxx-x86.h (elf_x86_link_hash_table): Remove dt_reloc,
	dt_reloc_sz and dt_reloc_ent.
	* elf-vxworks.c (_bfd_elf_maybe_vxworks_add_dynamic_tags): New.
	* elf-vxworks.h (_bfd_elf_maybe_vxworks_add_dynamic_tags):
	Likewise.
	* elf32-hppa.c (elf32_hppa_link_hash_table_create): Set
	etab.dt_pltgot_required.
	(elf32_hppa_size_dynamic_sections): Call
	_bfd_elf_add_dynamic_tags.
	* elf32-metag.c (elf_metag_link_hash_table_create): Set
	etab.dt_pltgot_required.
	(elf_metag_size_dynamic_sections): Call _bfd_elf_add_dynamic_tags.
	* elf32-sh.c (sh_elf_link_hash_table_create): Set
	root.dt_pltgot_required for FDPIC output.
	(sh_elf_size_dynamic_sections): Call
	_bfd_elf_maybe_vxworks_add_dynamic_tags.
	* elf32-xtensa.c (elf_xtensa_link_hash_table_create): Set
	elf.dt_pltgot_required.
	(elf_xtensa_size_dynamic_sections): Call
	_bfd_elf_add_dynamic_tags.
	* elf64-hppa.c (elf64_hppa_hash_table_create): Set
	root.dt_pltgot_required.
	(elf64_hppa_size_dynamic_sections): Call
	_bfd_elf_add_dynamic_tags.
	* elfnn-ia64.c (elfNN_ia64_hash_table_create): Set
	root.dt_pltgot_required.
	(elfNN_ia64_size_dynamic_sections): Set root.dt_jmprel_required
	for rel_pltoff_sec.  Call _bfd_elf_add_dynamic_tags.
	* elflink.c (_bfd_elf_add_dynamic_tags): New.
 2020-06-23 05:07:45 -07:00
Nelson Chu
39ff0b8123 RISC-V: Report warning when linking the objects with different priv specs. 
We do know some conflicts among different privileged specs.  For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts.  But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems.  But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs.  But the option
is still under discussion.

Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs.  This not only makes the linker more flexible,
but also warns people that the conflicts may happen.  We also need to update
the output priv spec version once the input priv spec is newer.

	bfd/
	* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
	opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
	(riscv_get_priv_spec_class): Likewise.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New function, convert
	the version numbers into string, then call riscv_get_priv_spec_class
	to get the priv spec class.
	* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
	from include/opcode/riscv.h to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New forward declaration.
	(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
	* elfnn-riscv.c (riscv_merge_attributes):  Get the priv spec classes
	of input and output objects form their priv spec attributes by
	riscv_get_priv_spec_class_from_numbers.  Report warning rather than
	errors when linking objects with differnet priv spec versions.  We do
	know v1.9.1 may have conflicts to other versions, so report the
	warning, too.  After that, update the output priv spec version to the
	newest one so far.

	gas/
	* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
	(riscv_set_default_priv_spec): Get the priv spec version from the
	priv spec attributes by riscv_get_priv_spec_class_from_numbers.

	include/
	* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
	forward declarations to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.

	opcodes/
	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
 2020-06-22 10:01:14 +08:00
Nelson Chu
cbd7581f34 RISC-V: Don't assume the priv attributes are in order when handling them. 
There is no guarantee that the priv attributes should be defined in order.
Therefore, we shouldn't have the order assumption when handling them in the
riscv_merge_attributes.  Set priv_attrs_merged to TRUE if we have handled
all of the priv attributes.

	bfd/
	* elfnn-riscv.c (riscv_merge_attributes): Once we meet one of the
	priv attributes, we will check the conflicts for all of them (major,
	minor and revision), and then set the priv_attrs_merged to TRUE to
	indicate that we have handled all of the priv attributes.  Remove
	the unused boolean priv_may_conflict, in_priv_zero and out_priv_zero.
 2020-06-22 09:54:02 +08:00
Nelson Chu
412857647f RISC-V: The object without priv spec attributes can be linked with any object. 
bfd/
	* elfnn-riscv.c (riscv_merge_attributes): Add new boolean
	priv_may_conflict, in_priv_zero and out_priv_zero to decide whether
	the object can be linked according to it's priv attributes.  The object
	without any priv spec attributes can be linked with others.  If the first
	input object doesn't contain any priv attributes, then we need to copy
	the setting from the next input one.  Also report more detailed error
	messages to user.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Rename to
	attr-merge-priv-spec-01.d.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-c.s: Set priv spec
	to 1.11.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-d.s: Empty priv spec
	setting.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: New testcase.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2020-06-05 12:20:53 +08:00
H.J. Lu
d49e5065ed ELF: Consolidate maybe_set_textrel 
All maybe_set_textrel implementations are the same.  Consolidate them
to a single _bfd_elf_maybe_set_textrel.

	* elf-bfd.h (_bfd_elf_maybe_set_textrel): New
	* elf32-arm.c (maybe_set_textrel): Removed.
	(elf32_arm_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-csky.c (maybe_set_textrel): Removed.
	(csky_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-hppa.c (maybe_set_textrel): Removed.
	(elf32_hppa_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-lm32.c (maybe_set_textrel): Removed.
	(lm32_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-m32r.c (maybe_set_textrel): Removed.
	(m32r_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-metag.c (maybe_set_textrel): Removed.
	(elf_metag_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-nds32.c (maybe_set_textrel): Removed.
	(nds32_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-or1k.c (maybe_set_textrel): Removed.
	(or1k_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-ppc.c (maybe_set_textrel): Removed.
	(ppc_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-s390.c (maybe_set_textrel): Removed.
	(elf_s390_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-sh.c (maybe_set_textrel): Removed.
	(sh_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-tic6x.c (maybe_set_textrel): Removed.
	(elf32_tic6x_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf32-tilepro.c (maybe_set_textrel): Removed.
	(tilepro_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf64-ppc.c (maybe_set_textrel): Removed.
	(ppc64_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elf64-s390.c (maybe_set_textrel): Removed.
	(elf_s390_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elfnn-aarch64.c (maybe_set_textrel): Removed.
	(elfNN_aarch64_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elfnn-riscv.c (maybe_set_textrel): Removed.
	(riscv_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elfxx-sparc.c (maybe_set_textrel): Removed.
	(_bfd_sparc_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elfxx-tilegx.c (maybe_set_textrel): Removed.
	(tilegx_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elfxx-x86.c (maybe_set_textrel): Removed.
	(_bfd_x86_elf_size_dynamic_sections): Replace maybe_set_textrel
	with _bfd_elf_maybe_set_textrel.
	* elflink.c (_bfd_elf_maybe_set_textrel): New.
 2020-06-03 07:07:24 -07:00
H.J. Lu
ad172eaa4f ELF: Copy dyn_relocs in _bfd_elf_link_hash_copy_indirect 
Copy dyn_relocs in _bfd_elf_link_hash_copy_indirect instead of in each
target backend.

	PR ld/26067
	* elf32-arm.c (elf32_arm_copy_indirect_symbol): Don't copy
	dyn_relocs.
	* elf32-csky.c (csky_elf_copy_indirect_symbol): Likewise.
	* elf32-hppa.c (elf32_hppa_copy_indirect_symbol): Likewise.
	* elf32-metag.c (elf_metag_copy_indirect_symbol): Likewise.
	* elf32-microblaze.c (microblaze_elf_copy_indirect_symbol):
	Likewise.
	* elf32-nds32.c (nds32_elf_copy_indirect_symbol): Likewise.
	* elf32-nios2.c (nios2_elf32_copy_indirect_symbol): Likewise.
	* elf32-or1k.c (or1k_elf_copy_indirect_symbol): Likewise.
	* elf32-s390.c (elf_s390_copy_indirect_symbol): Likewise.
	* elf32-sh.c (sh_elf_copy_indirect_symbol): Likewise.
	* elf32-tilepro.c (tilepro_elf_copy_indirect_symbol): Likewise.
	* elf64-s390.c (elf_s390_copy_indirect_symbol): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_copy_indirect_symbol): Likewise.
	* elfnn-riscv.c (riscv_elf_copy_indirect_symbol): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_copy_indirect_symbol): Likewise.
	* elfxx-tilegx.c (tilegx_elf_copy_indirect_symbol): Likewise.
	* elfxx-x86.c (_bfd_x86_elf_copy_indirect_symbol): Likewise.
	* elf32-lm32.c (lm32_elf_copy_indirect_symbol): Removed.
	(elf_backend_copy_indirect_symbol): Likewise.
	* elf32-m32r.c (m32r_elf_copy_indirect_symbol): Removed.
	(elf_backend_copy_indirect_symbol): Likewise.
	* elflink.c (_bfd_elf_link_hash_copy_indirect): Copy dyn_relocs.
 2020-06-03 07:03:59 -07:00
H.J. Lu
5dbc8b372f ELF: Consolidate readonly_dynrelocs 
All readonly_dynrelocs implementations are the same.  Consolidate them
to a single _bfd_elf_readonly_dynrelocs.

	PR ld/26067
	* elf-bfd.h (_bfd_elf_readonly_dynrelocs): New.
	* elf32-arm.c (readonly_dynrelocs): Removed.
	(maybe_set_textrel): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	* elf32-csky.c (readonly_dynrelocs): Removed.
	(maybe_set_textrel): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	*  elf32-hppa.c(readonly_dynrelocs): Removed.
	(alias_readonly_dynrelocs): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-lm32.c (readonly_dynrelocs): Removed.
	(lm32_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-m32r.c (readonly_dynrelocs): Removed.
	(m32r_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-metag.c (readonly_dynrelocs): Removed.
	(elf_metag_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-microblaze.c (readonly_dynrelocs): Removed.
	(microblaze_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	* elf32-nds32.c (readonly_dynrelocs): Removed.
	(nds32_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-or1k.c (readonly_dynrelocs): Removed.
	(or1k_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	* elf32-ppc.c (readonly_dynrelocs): Removed.
	(alias_readonly_dynrelocs): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	(ppc_elf_adjust_dynamic_symbol): Likewise.
	(maybe_set_textrel): Likewise.
	* elf32-s390.c (readonly_dynrelocs): Removed.
	(elf_s390_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-sh.c (readonly_dynrelocs): Removed.
	(sh_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf32-tic6x.c (readonly_dynrelocs): Removed.
	(maybe_set_textrel): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	* elf32-tilepro.c (readonly_dynrelocs): Removed.
	(tilepro_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elf64-ppc.c (readonly_dynrelocs): Removed.
	(alias_readonly_dynrelocs): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	(ppc64_elf_adjust_dynamic_symbol): Likewise.
	(maybe_set_textrel): Likewise.
	* elf64-s390.c (readonly_dynrelocs): Removed.
	(elf_s390_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elflink.c (_bfd_elf_readonly_dynrelocs): New.
	* elfnn-aarch64.c (readonly_dynrelocs): Removed.
	(maybe_set_textrel): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	* elfnn-riscv.c (readonly_dynrelocs): Removed.
	(riscv_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elfxx-sparc.c (readonly_dynrelocs): Removed.
	(_bfd_sparc_elf_adjust_dynamic_symbol): Replace
	readonly_dynrelocs with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elfxx-tilegx.c (readonly_dynrelocs): Removed.
	(tilegx_elf_adjust_dynamic_symbol): Replace readonly_dynrelocs
	with _bfd_elf_readonly_dynrelocs.
	(maybe_set_textrel): Likewise.
	* elfxx-x86.c (readonly_dynrelocs): Removed.
	(maybe_set_textrel): Replace readonly_dynrelocs with
	_bfd_elf_readonly_dynrelocs.
	(_bfd_x86_elf_adjust_dynamic_symbol): Likewise.
 2020-06-03 07:01:13 -07:00
H.J. Lu
190eb1ddba ELF: Move dyn_relocs to struct elf_link_hash_entry 
All ELF backends with shared library support have

  /* Track dynamic relocs copied for this symbol.  */
  struct elf_dyn_relocs *dyn_relocs;

in symbol hash entry.  Move dyn_relocs to struct elf_link_hash_entry
to reduce code duplication.

	PR ld/26067
	* elf-bfd.h (elf_link_hash_entry): Add dyn_relocs after size.
	* elf-s390-common.c (s390_elf_allocate_ifunc_dyn_relocs):
	Updated.
	* elf32-arc.c (elf_arc_link_hash_entry): Remove dyn_relocs.
	(elf_arc_link_hash_newfunc): Updated.
	* elf32-arm.c (elf32_arm_link_hash_entry): Remove dyn_relocs.
	(elf32_arm_link_hash_newfunc): Updated.
	(elf32_arm_copy_indirect_symbol): Likewise.
	(elf32_arm_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs_for_symbol): Likewise.
	* elf32-csky.c (csky_elf_link_hash_entry): Remove dyn_relocs.
	(csky_elf_link_hash_newfunc): Updated.
	(csky_allocate_dynrelocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(csky_elf_copy_indirect_symbol): Likewise.
	* elf32-hppa.c (elf32_hppa_link_hash_entry): Remove dyn_relocs.
	(hppa_link_hash_newfunc): Updated.
	(elf32_hppa_copy_indirect_symbol): Likewise.
	(elf32_hppa_hide_symbol): Likewise.
	(elf32_hppa_adjust_dynamic_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	(elf32_hppa_relocate_section): Likewise.
	* elf32-i386.c (elf_i386_check_relocs): Likewise.
	* elf32-lm32.c (elf_lm32_link_hash_entry): Removed.
	(lm32_elf_link_hash_newfunc): Likewise.
	(lm32_elf_link_hash_table_create): Updated.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	(lm32_elf_copy_indirect_symbol): Likewise.
	* elf32-m32r.c (elf_m32r_link_hash_entry): Removed.
	(m32r_elf_link_hash_newfunc): Likewise.
	(m32r_elf_link_hash_table_create): Updated.
	(m32r_elf_copy_indirect_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf32-metag.c (elf_metag_link_hash_entry): Remove dyn_relocs.
	(metag_link_hash_newfunc): Updated.
	(elf_metag_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf32-microblaze.c (elf32_mb_link_hash_entry): Remove
	dyn_relocs.
	(link_hash_newfunc): Updated.
	(microblaze_elf_check_relocs): Likewise.
	(microblaze_elf_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf32-nds32.c (elf_nds32_link_hash_entry): Remove dyn_relocs.
	(nds32_elf_link_hash_newfunc): Updated.
	(nds32_elf_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	(nds32_elf_check_relocs): Likewise.
	* elf32-nios2.c (elf32_nios2_link_hash_entry): Remove dyn_relocs.
	(link_hash_newfunc): Updated.
	(nios2_elf32_copy_indirect_symbol): Likewise.
	(nios2_elf32_check_relocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf32-or1k.c (elf_or1k_link_hash_entry): Remove dyn_relocs.
	(or1k_elf_link_hash_newfunc): Updated.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	(or1k_elf_copy_indirect_symbol): Likewise.
	* elf32-ppc.c (ppc_elf_link_hash_entry): Remove dyn_relocs.
	(ppc_elf_link_hash_newfunc): Updated.
	(ppc_elf_copy_indirect_symbol): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(ppc_elf_adjust_dynamic_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	* elf32-s390.c (elf_s390_link_hash_entry): Remove dyn_relocs.
	(link_hash_newfunc): Updated.
	(elf_s390_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(elf_s390_adjust_dynamic_symbol): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf32-sh.c (elf_sh_link_hash_entry): Remove dyn_relocs.
	(sh_elf_link_hash_newfunc): Updated.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	(sh_elf_copy_indirect_symbol): Likewise.
	(sh_elf_check_relocs): Likewise.
	* elf32-tic6x.c (elf32_tic6x_link_hash_entry): Removed.
	(elf32_tic6x_link_hash_newfunc): Likewise.
	(elf32_tic6x_link_hash_table_create): Updated.
	(readonly_dynrelocs): Likewise.
	(elf32_tic6x_check_relocs): Likewise.
	(elf32_tic6x_allocate_dynrelocs): Likewise.
	* elf32-tilepro.c (tilepro_elf_link_hash_entry): Remove
	dyn_relocs.
	(link_hash_newfunc): Updated.
	(tilepro_elf_copy_indirect_symbol): Likewise.
	(tilepro_elf_check_relocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf64-ppc.c (ppc_link_hash_entry): Remove dyn_relocs.
	(ppc64_elf_copy_indirect_symbol): Updated.
	(ppc64_elf_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(ppc64_elf_adjust_dynamic_symbol): Likewise.
	(dec_dynrel_count): Likewise.
	(allocate_dynrelocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* elf64-s390.c (elf_s390_link_hash_entry): Remove dyn_relocs.
	(link_hash_newfunc): Updated.
	(elf_s390_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
	* elfnn-aarch64.c (elf_aarch64_link_hash_entry): Remove
	dyn_relocs.
	(elfNN_aarch64_link_hash_newfunc): Updated.
	(elfNN_aarch64_copy_indirect_symbol): Likewise.
	(readonly_dynrelocs): Likewise.
	(need_copy_relocation_p): Likewise.
	(elfNN_aarch64_allocate_dynrelocs): Likewise.
	(elfNN_aarch64_allocate_ifunc_dynrelocs): Likewise.
	* elfnn-riscv.c (riscv_elf_link_hash_entry): Remove dyn_relocs.
	(link_hash_newfunc): Updated.
	(riscv_elf_copy_indirect_symbol): Likewise.
	(riscv_elf_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_link_hash_entry): Remove
	dyn_relocs.
	(link_hash_newfunc): Updated.
	(_bfd_sparc_elf_copy_indirect_symbol): Likewise.
	(_bfd_sparc_elf_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elfxx-tilegx.c (tilegx_elf_link_hash_entry): Remove dyn_relocs.
	(link_hash_newfunc): Updated.
	(tilegx_elf_copy_indirect_symbol): Likewise.
	(tilegx_elf_check_relocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(allocate_dynrelocs): Likewise.
	* elfxx-x86.c (elf_x86_allocate_dynrelocs): Likewise.
	(readonly_dynrelocs): Likewise.
	(_bfd_x86_elf_copy_indirect_symbol): Likewise.
	* elfxx-x86.h (elf_x86_link_hash_entry): Remove dyn_relocs.
 2020-06-01 18:19:05 -07:00
Alan Modra
c95949892f Replace "if (x) free (x)" with "free (x)", bfd 
* aoutx.h: Replace "if (x) free (x)" with "free (x)" throughout.
	* archive.c, * bfd.c, * bfdio.c, * coff-alpha.c, * coff-ppc.c,
	* coff-sh.c, * coff-stgo32.c, * coffcode.h, * coffgen.c,
	* cofflink.c, * cpu-arm.c, * doc/chew.c, * dwarf2.c, * ecoff.c,
	* ecofflink.c, * elf-eh-frame.c, * elf-m10200.c, * elf-m10300.c,
	* elf-strtab.c, * elf.c, * elf32-arc.c, * elf32-arm.c,
	* elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-crx.c,
	* elf32-epiphany.c, * elf32-ft32.c, * elf32-h8300.c,
	* elf32-ip2k.c, * elf32-m32c.c, * elf32-m68hc11.c,
	* elf32-m68k.c, * elf32-microblaze.c, * elf32-msp430.c,
	* elf32-nds32.c, * elf32-nios2.c, * elf32-ppc.c, * elf32-pru.c,
	* elf32-rl78.c, * elf32-rx.c, * elf32-sh.c, * elf32-spu.c,
	* elf32-v850.c, * elf32-xtensa.c, * elf64-alpha.c,
	* elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c
	* elf64-mmix.c, * elf64-ppc.c, * elf64-sparc.c, * elfcode.h,
	* elflink.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-mips.c,
	* elfxx-x86.c, * format.c, * ihex.c, * libbfd.c, * linker.c,
	* mmo.c, * opncls.c, * pdp11.c, * peXXigen.c, * pef.c,
	* peicode.h, * simple.c, * som.c, * srec.c, * stabs.c, * syms.c,
	* targets.c, * vms-lib.c, * xcofflink.c, * xtensa-isa.c: Likewise.
 2020-05-21 10:11:57 +09:30
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
 2020-05-20 17:22:48 +01:00
Nelson Chu
fc46e8bd35 RISC-V: Add elfNN_riscv_mkobject to initialize RISC-V tdata. 
For now we only have one char pointer in RISC-V tdata, so it should be fine.
But once we need more elements in tdata, then we may get some uninitialize
or unexpected values.  I do meet the same problem when extending the RISC-V
tdata.

	bfd/
	elfnn-riscv.c (elfNN_riscv_mkobject):  New function.  We need this
	to initialize RISC-V tdata.
 2020-05-14 10:39:54 +08:00
Alan Modra
a2714d6cca PR25900, RISC-V: null pointer dereference 
PR 25900
	* elfnn-riscv.c (_bfd_riscv_relax_section): Check root.type before
	accessing root.u.def of symbols.  Also check root.u.def.section
	is non-NULL.  Reverse tests so as to make the logic positive.
 2020-05-01 15:32:36 +09:30
Alan Modra
dc1e8a474f Indent labels 
Labels don't go in the first column according to standard emacs C
indent rules, and I got annoyed enough at seeing diff -p show a label
rather than the function name to fix this.

bfd/
	* aoutx.h: Indent labels correctly.  Format error strings.
	* archive.c: Likewise.
	* archive64.c: Likewise.
	* coff-arm.c: Likewise.
	* coff-rs6000.c: Likewise.
	* coff-stgo32.c: Likewise.
	* cpu-arm.c: Likewise.
	* dwarf2.c: Likewise.
	* elf-ifunc.c: Likewise.
	* elf-properties.c: Likewise.
	* elf-s390-common.c: Likewise.
	* elf-strtab.c: Likewise.
	* elf.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-cr16.c: Likewise.
	* elf32-csky.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-msp430.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-pru.c: Likewise.
	* elf32-xtensa.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elfcode.h: Likewise.
	* elfcore.h: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfnn-riscv.c: Likewise.
	* elfxx-mips.c: Likewise.
	* elfxx-sparc.c: Likewise.
	* elfxx-x86.c: Likewise.
	* i386lynx.c: Likewise.
	* merge.c: Likewise.
	* pdp11.c: Likewise.
	* plugin.c: Likewise.
	* reloc.c: Likewise.
binutils/
	* elfedit.c: Indent labels correctly.
	* readelf.c: Likewise.
	* resres.c: Likewise.
gas/
	* config/obj-elf.c: Indent labels correctly.
	* config/obj-macho.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-frv.c: Likewise.
	* config/tc-i386-intel.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-riscv.c: Likewise.
	* config/tc-s12z.c: Likewise.
	* config/tc-xtensa.c: Likewise.
	* config/tc-z80.c: Likewise.
	* read.c: Likewise.
	* symbols.c: Likewise.
	* write.c: Likewise.
ld/
	* emultempl/cskyelf.em: Indent labels correctly.
	* ldfile.c: Likewise.
	* ldlang.c: Likewise.
	* plugin.c: Likewise.
opcodes/
	* aarch64-asm.c: Indent labels correctly.
	* aarch64-dis.c: Likewise.
	* aarch64-gen.c: Likewise.
	* aarch64-opc.c: Likewise.
	* alpha-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* nds32-asm.c: Likewise.
	* nfp-dis.c: Likewise.
	* visium-dis.c: Likewise.
 2020-02-26 10:37:25 +10:30
Alan Modra
986f078366 bfd_size_type to size_t 
bfd_size_type was invented a long time ago in the K&R days.  Many
places in binutils ought to be using size_t instead (and there are
lots of places that use long or unsigned long that really ought to use
size_t too).  Note that you can't change everything over to size_t: A
32-bit host needs a larger type than size_t to support reading and
processing of 64-bit ELF object files.  This patch just tidies some
of the more obvious uses of bfd_size_type that could be size_t.  There
no doubt are more lurking in the source.  Incidentally, practically
all functions used for output of object files can use size_t and don't
need to worry about overflow of size expressions.  If you have
something like
  symcount * sizeof (void *)
when symcount is counting symbols already in memory then you know that
this expression can't overflow since the size of a symbol in memory is
larger by far than that of a pointer.

	* aix386-core.c (aix386_core_file_p): Use size_t for "amt".
	* aout-target.h (object_p): Likewise.
	* aout-tic30.c (tic30_aout_object_p): Likewise.
	* aoutx.h (some_aout_object_p, mkobject, make_empty_symbol),
	(emit_stringtab, write_syms, link_hash_table_create),
	(aout_link_write_other_symbol): Likewise.
	* archive.c (_bfd_generic_mkarchive, bfd_generic_archive_p),
	(bfd_ar_hdr_from_filesystem, _bfd_write_archive_contents),
	(_bfd_compute_and_write_armap): Likewise.
	* archures.c (bfd_arch_list): Likewise.
	* bfd.c (bfd_record_phdr): Likewise.
	* binary.c (binary_canonicalize_symtab): Likewise.
	* cisco-core.c (cisco_core_file_validate): Likewise.
	* coff-arm.c (coff_arm_link_hash_table_create, find_thumb_glue),
	(find_arm_glue, record_arm_to_thumb_glue),
	(record_thumb_to_arm_glue): Likewise.
	* coff-ppc.c (ppc_coff_link_hash_table_create, record_toc),
	(ppc_allocate_toc_section): Likewise.
	* coff-rs6000.c (_bfd_xcoff_mkobject, _bfd_xcoff_archive_p): Likewise.
	* coff-sh.c (sh_relax_section): Likewise.
	* coff64-rs6000.c (xcoff64_archive_p): Likewise.
	* coffcode.h (handle_COMDAT, coff_new_section_hook),
	(coff_set_alignment_hook, coff_mkobject),
	(coff_compute_section_file_positions): Likewise.
	* coffgen.c (coff_make_empty_symbol, coff_bfd_make_debug_symbol),
	(coff_find_nearest_line_with_names),
	( bfd_coff_set_symbol_class): Likewise.
	* cofflink.c (_bfd_coff_link_hash_table_create),
	(_bfd_coff_link_input_bfd): Likewise.
	* dwarf1.c (alloc_dwarf1_unit, alloc_dwarf1_func): Likewise.
	* dwarf2.c (read_abbrevs, read_attribute_value, add_line_info),
	(build_line_info_table, sort_line_sequences),
	(line_info_add_include_dir, line_info_add_file_name),
	(decode_line_info, scan_unit_for_symbols, parse_comp_unit),
	(place_sections, _bfd_dwarf2_slurp_debug_info): Likewise.
	* ecoff.c (_bfd_ecoff_mkobject, _bfd_ecoff_make_empty_symbol),
	(_bfd_ecoff_find_nearest_line),
	(_bfd_ecoff_bfd_link_hash_table_create): Likewise.
	* ecofflink.c (bfd_ecoff_debug_init): Likewise.
	* elf-hppa.h (_bfd_elf_hppa_gen_reloc_type): Likewise.
	* elf-m10300.c (mn10300_elf_relax_section),
	(elf32_mn10300_link_hash_table_create): Likewise.
	* elf-strtab.c (_bfd_elf_strtab_init): Likewise.
	* elf.c (make_mapping, copy_elf_program_header): Likewise.
	* elf32-arm.c (elf32_arm_link_hash_table_create),
	(elf32_arm_setup_section_lists, elf32_arm_check_relocs),
	(elf32_arm_new_section_hook): Likewise.
	* elf32-avr.c (elf_avr_new_section_hook),
	(elf32_avr_link_hash_table_create, get_local_syms),
	(elf32_avr_setup_section_lists): Likewise.
	* elf32-bfin.c (bfinfdpic_elf_link_hash_table_create),
	(bfin_link_hash_table_create): Likewise.
	* elf32-cr16.c (elf32_cr16_link_hash_table_create): Likewise.
	* elf32-cris.c (elf_cris_link_hash_table_create): Likewise.
	* elf32-csky.c (csky_elf_link_hash_table_create),
	(csky_elf_check_relocs, elf32_csky_setup_section_lists): Likewise.
	* elf32-frv.c (frvfdpic_elf_link_hash_table_create): Likewise.
	* elf32-hppa.c (elf32_hppa_link_hash_table_create),
	(elf32_hppa_setup_section_lists, get_local_syms): Likewise.
	* elf32-i386.c (elf_i386_check_relocs): Likewise.
	* elf32-lm32.c (lm32_elf_link_hash_table_create): Likewise.
	* elf32-m32r.c (m32r_elf_link_hash_table_create),
	(m32r_elf_check_relocs): Likewise.
	* elf32-m68hc1x.c (m68hc11_elf_hash_table_create),
	(elf32_m68hc11_setup_section_lists),
	(elf32_m68hc11_size_stubs): Likewise.
	* elf32-m68k.c (elf_m68k_link_hash_table_create): Likewise.
	* elf32-metag.c (elf_metag_link_hash_table_create),
	(elf_metag_setup_section_lists): Likewise.
	* elf32-microblaze.c (microblaze_elf_link_hash_table_create),
	(microblaze_elf_check_relocs): Likewise.
	* elf32-nds32.c (nds32_elf_link_hash_table_create),
	(nds32_elf_check_relocs): Likewise.
	* elf32-nios2.c (nios2_elf32_setup_section_lists),
	(get_local_syms, nios2_elf32_check_relocs),
	(nios2_elf32_link_hash_table_create): Likewise.
	* elf32-or1k.c (or1k_elf_link_hash_table_create),
	(or1k_elf_check_relocs): Likewise.
	* elf32-ppc.c (ppc_elf_modify_segment_map, update_plt_info): Likewise.
	* elf32-pru.c (pru_elf32_link_hash_table_create): Likewise.
	* elf32-s390.c (elf_s390_link_hash_table_create),
	(elf_s390_check_relocs): Likewise.
	* elf32-score.c (score_elf_create_got_section),
	(s3_elf32_score_new_section_hook),
	(elf32_score_link_hash_table_create): Likewise.
	* elf32-score7.c (score_elf_create_got_section),
	(s7_elf32_score_new_section_hook): Likewise.
	* elf32-sh.c (sh_elf_link_hash_table_create),
	(sh_elf_check_relocs): Likewise.
	* elf32-tic6x.c (elf32_tic6x_link_hash_table_create),
	(elf32_tic6x_new_section_hook, elf32_tic6x_check_relocs): Likewise.
	* elf32-tilepro.c (tilepro_elf_link_hash_table_create),
	(tilepro_elf_check_relocs): Likewise.
	* elf32-v850.c (remember_hi16s_reloc): Likewise.
	* elf32-vax.c (elf_vax_link_hash_table_create): Likewise.
	* elf32-xtensa.c (elf_xtensa_link_hash_table_create),
	(elf_xtensa_new_section_hook): Likewise.
	* elf64-alpha.c (elf64_alpha_bfd_link_hash_table_create),
	(get_got_entry, elf64_alpha_check_relocs): Likewise.
	* elf64-hppa.c (elf64_hppa_hash_table_create): Likewise.
	* elf64-ia64-vms.c (elf64_ia64_object_p): Likewise.
	* elf64-mmix.c (mmix_elf_new_section_hook): Likewise.
	* elf64-ppc.c (ppc64_elf_new_section_hook),
	(ppc64_elf_link_hash_table_create, update_local_sym_info),
	(update_plt_info, ppc64_elf_check_relocs): Likewise.
	* elf64-s390.c (elf_s390_link_hash_table_create),
	(elf_s390_check_relocs): Likewise.
	* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
	* elflink.c (bfd_elf_link_record_local_dynamic_symbol),
	(_bfd_elf_link_find_version_dependencies, elf_link_add_object_symbols),
	(elf_link_add_archive_symbols, compute_bucket_count),
	(bfd_elf_size_dynsym_hash_dynstr, _bfd_elf_link_hash_table_create),
	(bfd_elf_get_bfd_needed_list, elf_link_swap_symbols_out),
	(bfd_elf_final_link): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_link_hash_table_create),
	(elfNN_aarch64_setup_section_lists, elfNN_aarch64_check_relocs),
	(elfNN_aarch64_new_section_hook): Likewise.
	* elfnn-ia64.c (elfNN_ia64_object_p): Likewise.
	* elfnn-riscv.c (riscv_elf_link_hash_table_create),
	(riscv_elf_check_relocs): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_new_section_hook),
	(_bfd_mips_elf_add_symbol_hook, _bfd_mips_elf_check_relocs),
	(_bfd_mips_elf_modify_segment_map, _bfd_mips_elf_set_section_contents),
	(_bfd_mips_elf_link_hash_table_create): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_link_hash_table_create),
	(_bfd_sparc_elf_check_relocs),
	(_bfd_sparc_elf_new_section_hook): Likewise.
	* elfxx-tilegx.c (tilegx_elf_link_hash_table_create),
	(tilegx_elf_check_relocs): Likewise.
	* elfxx-x86.c (_bfd_x86_elf_link_hash_table_create): Likewise.
	* format.c (bfd_check_format_matches): Likewise.
	* hash.c (_bfd_stringtab_init): Likewise.
	* ihex.c (ihex_scan): Likewise.
	* irix-core.c (irix_core_core_file_p): Likewise.
	* linker.c (bfd_wrapped_link_hash_lookup),
	(_bfd_generic_link_hash_table_create),
	(_bfd_generic_reloc_link_order): Likewise.
	* lynx-core.c (lynx_core_file_p): Likewise.
	* netbsd-core.c (netbsd_core_file_p): Likewise.
	* osf-core.c (osf_core_core_file_p): Likewise.
	* pdp11.c (some_aout_object_p, mkobject, make_empty_symbol),
	(link_hash_table_create, aout_link_write_other_symbol): Likewise.
	* peXXigen.c (_bfd_XX_bfd_copy_private_section_data): Likewise.
	* peicode.h (pe_mkobject): Likewise.
	* ppcboot.c (ppcboot_mkobject, ppcboot_canonicalize_symtab): Likewise.
	* ptrace-core.c (ptrace_unix_core_file_p): Likewise.
	* sco5-core.c (read_uarea): Likewise.
	* som.c (hppa_som_gen_reloc_type, som_object_p, som_prep_headers),
	(som_write_fixups, som_write_space_strings, som_write_symbol_strings),
	(som_finish_writing, som_canonicalize_symtab, som_new_section_hook),
	(som_bfd_copy_private_section_data, bfd_som_set_section_attributes),
	(bfd_som_attach_aux_hdr, som_write_armap): Likewise.
	* srec.c (srec_scan): Likewise.
	* syms.c (_bfd_generic_make_empty_symbol): Likewise.
	* targets.c (bfd_target_list): Likewise.
	* tekhex.c (first_phase, tekhex_sizeof_headers): Likewise.
	* trad-core.c (trad_unix_core_file_p): Likewise.
	* vms-alpha.c (vms_initialize, alpha_vms_bfd_link_hash_table_create),
	(vms_new_section_hook): Likewise.
	* wasm-module.c (wasm_make_empty_symbol): Likewise.
	* xcofflink.c (xcoff_get_section_contents),
	(_bfd_xcoff_bfd_link_hash_table_create, xcoff_set_import_path),
	(xcoff_find_function, bfd_xcoff_link_record_set, xcoff_build_ldsym),
	(bfd_xcoff_size_dynamic_sections, xcoff_link_input_bfd): Likewise.
 2020-02-19 13:12:00 +10:30
Jim Wilson
403d1bd91d RISC-V: Change -march parsing. 
bfd/
	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
	* bfd/elfnn-riscv.c (riscv_skip_prefix): New.
	(riscv_prefix_cmp): Likewise.
	(riscv_non_std_ext_p): Deleted.
	(riscv_std_sv_ext_p): Likewise.
	(riscv_non_std_sv_ext_p): Likewise.
	(riscv_merge_non_std_and_sv_ext): Rename to...
	(riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp.
	(riscv_merge_arch_attr_info): Replace 3 calls to
	riscv_merge_non_std_and_sv_ext with single call to
	riscv_merge_multi_letter_ext.
	* bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we
	encounter a 'z' prefix.
	(riscv_get_prefix_class): New function, return prefix class based
	on first few characters of input string.
	(riscv_parse_config): New structure to factor out minor differences
	in extension class parsing behaviour.
	(riscv_parse_sv_or_non_std_ext): Rename to...
	(riscv_parse_prefixed_ext): and parameterise with
	riscv_parse_config.
	(riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New.
	(riscv_multi_letter_ext_valid_p): New.
	(riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New.
	(riscv_parse_subset): Delegate all non-single-letter parsing work
	to riscv_parse_prefixed_ext.
	* bfd/elfxx-riscv.h (riscv_isa_ext_class): New type.
	(riscv_get_prefix_class): Declare.

	gas/
	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
	* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
	s exts must be known, so rename *ok* to *fail*.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
	* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
	above change.
	* testsuite/gas/riscv/march-fail-sx.l: Likewise.
	* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.

Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
 2020-01-22 16:45:04 -08:00