The commit c144f63833 removed INSN_CLASS_A and
added INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC instead,
which broke the build of the sim for riscv targets.
Fix that by using the new INSN_CLASS types.
Fixes: c144f63833 ("RISC-V: Support B, Zaamo and Zalrsc extensions.")
Approved-By: Tom Tromey <tom@tromey.com>
There was apparently a confusion which cpu model uses
compressed JAL and which ADDIW. Fixed that in execute_c,
case MATCH_C_JAL | MATCH_C_ADDIW.
Fixes 3224e32fb8 ("sim: riscv: Add support for compressed integer instructions")
Approved-By: Andrew Burgess <aburgess@redhat.com>
Various gcc test cases fail due to the stack
alignment of 16 bytes is expected by gcc,
causing issues mostly with vararg functions,
e.g.
FAIL: gcc.c-torture/execute/nest-align-1.c -O0 execution test
FAIL: gcc.c-torture/execute/nest-stdar-1.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-12.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-15.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-16.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-17.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-20.c -O0 execution test
FAIL: gcc.c-torture/execute/va-arg-26.c -O0 execution test
...
Approved-By: Andrew Burgess <aburgess@redhat.com>
The uncompressed EBREAK instruction does not work
correctly this way, and the comment saying that
GDB expects us to step over EBREAK is just wrong.
The PC was always 4 bytes too high, which skips one
instruction at break and step over commands, and
causes complete chaos. The compressed EBREAK was
already implemented correctly.
Tested by using gdb's "target sim" and single-stepping.
Approved-By: Andrew Burgess <aburgess@redhat.com>
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>
The match_never() function has been removed and thus step_once() crashes
during instruction decoding. Fixed it by checking for null pointer before
invoking function attached to match_func member of riscv_opcode structure
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written
before using it to calculate destination address.
This commit also improves testutils.inc for riscv; make use of
pushsection and popsection when adding things to .data, and setup the
%gp global pointer register within the 'start' macro.
Approved-By: Andrew Burgess <aburgess@redhat.com>
This commit is the result of running the gdb/copyright.py script,
which automated the update of the copyright year range for all
source files managed by the GDB project to be updated to include
year 2023.
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.
These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces. While gdb
uses these, the APIs are part of the sim, not gdb. Move the headers
out of the gdb/ include namespace and into sim/ instead.
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense. Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
When reading/writing arbitrary data to the system's memory, the unsigned
char pointer type doesn't make that much sense. Switch it to void so we
align a bit with standard C library read/write functions, and to avoid
having to sprinkle casts everywhere.
After this commit:
commit 0938b032da
Date: Wed Feb 2 10:06:15 2022 +0900
RISC-V: Add 'Zmmul' extension in assembler.
some instructions in the RISC-V simulator stopped working as a new
instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
instructions were moved into this class.
The simulator doesn't currently handle this instruction class, and so
the instructions will now cause an illegal instruction trap.
This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
ensures the affected instructions can be executed by the simulator.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andrew Burgess <aburgess@redhat.com>
This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).
sim/ChangeLog:
* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.
For the avoidance of doubt, all changes in this commits were
performed by the script.
The sim-basics.h is too big and includes too many things. This leads
to some arch's sim-main.h having circular loop issues with defs, and
makes it hard to separate out common objects from arch-specific defs.
By splitting up sim-basics.h and killing off sim-main.h, it'll make
it easier to separate out the two.
The defs.h header will take care of including the various config.h
headers. For now, it's just config.h, but we'll add more when we
integrate gnulib in.
This header should be used instead of config.h, and should be the
first include in every .c file. We won't rely on the old behavior
where we expected files to include the port's sim-main.h which then
includes the common sim-basics.h which then includes config.h. We
have a ton of code that includes things before sim-main.h, and it
sometimes needs to be that way. Creating a dedicated header avoids
the ordering mess and implicit inclusion that shows up otherwise.
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions. It also
covers 32-bit & 64-bit targets.
The unittest coverage is a bit weak atm, but should get better.
