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aarch64: add STEP2 feature and its associated registers

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AArch64 defines new registers for the feature step2 (Enhanced Software Step
Extension). step2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
This commit is contained in:
Matthieu Longo
2024-07-03 18:36:26 +01:00
parent 27e411ef5d
commit f83675969b
5 changed files with 13 additions and 0 deletions
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4
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l
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@@ -10,4 +10,8 @@
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
[^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0'
[^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
[^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1'
[^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Info: macro invoked from here

2
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d
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@@ -13,3 +13,5 @@ Disassembly of section \.text:
.*: d53e5260 mrs x0, vsesr_el3 .*: d53e5260 mrs x0, vsesr_el3
.*: d5139c80 msr spmzr_el0, x0 .*: d5139c80 msr spmzr_el0, x0
.*: d5339c80 mrs x0, spmzr_el0 .*: d5339c80 mrs x0, spmzr_el0
.*: d5100540 msr mdstepop_el1, x0
.*: d5300540 mrs x0, mdstepop_el1

3
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s
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@@ -8,3 +8,6 @@ rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1
/* System Performance Monitors Extension version 2. */ /* System Performance Monitors Extension version 2. */
rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1 rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1
/* Enhanced Software Step Extension. */
rw_sys_reg sys_reg=mdstepop_el1 xreg=x0 r=1 w=1

3
include/opcode/aarch64.h
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@@ -234,6 +234,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE2p1, AARCH64_FEATURE_SVE2p1,
/* RCPC3 instructions. */ /* RCPC3 instructions. */
AARCH64_FEATURE_RCPC3, AARCH64_FEATURE_RCPC3,
/* Enhanced Software Step Extension. */
AARCH64_FEATURE_STEP2,
/* Checked Pointer Arithmetic instructions. */ /* Checked Pointer Arithmetic instructions. */
AARCH64_FEATURE_CPA, AARCH64_FEATURE_CPA,
/* FAMINMAX instructions. */ /* FAMINMAX instructions. */
@@ -373,6 +375,7 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, FAMINMAX)\ | AARCH64_FEATBIT (X, FAMINMAX)\
| AARCH64_FEATBIT (X, E3DSE) \ | AARCH64_FEATBIT (X, E3DSE) \
| AARCH64_FEATBIT (X, SPMU2) \ | AARCH64_FEATBIT (X, SPMU2) \
| AARCH64_FEATBIT (X, STEP2) \
) )
/* Architectures are the sum of the base and extensions. */ /* Architectures are the sum of the base and extensions. */

1
opcodes/aarch64-sys-regs.def
View File

@@ -573,6 +573,7 @@
SYSREG ("mdrar_el1", CPENC (2,0,1,0,0), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("mdrar_el1", CPENC (2,0,1,0,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("mdscr_el1", CPENC (2,0,0,2,2), 0, AARCH64_NO_FEATURES) SYSREG ("mdscr_el1", CPENC (2,0,0,2,2), 0, AARCH64_NO_FEATURES)
SYSREG ("mdselr_el1", CPENC (2,0,0,4,2), F_ARCHEXT, AARCH64_FEATURE (DEBUGv8p9)) SYSREG ("mdselr_el1", CPENC (2,0,0,4,2), F_ARCHEXT, AARCH64_FEATURE (DEBUGv8p9))
SYSREG ("mdstepop_el1", CPENC (2,0,0,5,2), F_ARCHEXT, AARCH64_FEATURE (STEP2))
SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), 0, AARCH64_NO_FEATURES) SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), 0, AARCH64_NO_FEATURES)
SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), 0, AARCH64_NO_FEATURES) SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), 0, AARCH64_NO_FEATURES)
SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), 0, AARCH64_NO_FEATURES) SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), 0, AARCH64_NO_FEATURES)