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Fix amd64 dwarf register number mapping (MMX register and higher)

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Dwarf register numbers are defined in "System V Application Binary
Interface AMD64 Architecture Processor Supplement Draft Version 0.99.6"

The amd64_dwarf_regmap array is missing the 8 MMX registers in Figure
3.36: DWARF Register Number Mapping page 57.  This leads to a wrong
value for the registers past this point.

gdb/ChangeLog:

        Pushed by Joel Brobecker  <brobecker@adacore.com>.
        * amd64-tdep.c (amd64_dwarf_regmap array): Add missing MMX
        registers.

Tested on x86_64-linux.
This commit is contained in:
Pierre Muller
2014-11-28 19:21:58 +04:00
committed by Joel Brobecker
parent b2859a9a54
commit f7ca3fcfcc
2 changed files with 13 additions and 1 deletions
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8
gdb/amd64-tdep.c
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@@ -199,7 +199,13 @@ static int amd64_dwarf_regmap[] =
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
/* MMX Registers 0 - 7.
We have to handle those registers specifically, as their register
number within GDB depends on the target (or they may even not be
available at all). */
-1, -1, -1, -1, -1, -1, -1, -1,
/* Control and Status Flags Register. */
AMD64_EFLAGS_REGNUM,