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RISC-V: reduce redundancy in sign/zero extension macro insn handling

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Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold
riscv_ext()'s calls md_assemblef(), the first of which were entirely
identical, while the other pair differed in just a single character.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Jan Beulich
2023-11-24 09:53:55 +01:00
parent 27b33966b1
commit eb5e952f95
3 changed files with 8 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
gas/config/tc-riscv.c
View File

@@ -1960,16 +1960,9 @@ load_const (int reg, expressionS *ep)
static void static void
riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
{ {
if (sign) md_assemblef ("slli x%d, x%d, %#x", destreg, srcreg, shift);
{ md_assemblef ("sr%ci x%d, x%d, %#x",
md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); sign ? 'a' : 'l', destreg, destreg, shift);
md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
}
else
{
md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
}
} }
/* Expand RISC-V Vector macros into one or more instructions. */ /* Expand RISC-V Vector macros into one or more instructions. */
@@ -2093,8 +2086,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
riscv_call (rd, rs1, imm_expr, *imm_reloc); riscv_call (rd, rs1, imm_expr, *imm_reloc);
break; break;
case M_ZEXTH: case M_EXTH:
riscv_ext (rd, rs1, xlen - 16, false); riscv_ext (rd, rs1, xlen - 16, *ip->insn_mo->name == 's');
break; break;
case M_ZEXTW: case M_ZEXTW:
@@ -2105,10 +2098,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
riscv_ext (rd, rs1, xlen - 8, true); riscv_ext (rd, rs1, xlen - 8, true);
break; break;
case M_SEXTH:
riscv_ext (rd, rs1, xlen - 16, true);
break;
case M_VMSGE: case M_VMSGE:
vector_macro (ip); vector_macro (ip);
break; break;

3
include/opcode/riscv.h
View File

@@ -558,10 +558,9 @@ enum
M_CALL, M_CALL,
M_J, M_J,
M_LI, M_LI,
M_ZEXTH, M_EXTH,
M_ZEXTW, M_ZEXTW,
M_SEXTB, M_SEXTB,
M_SEXTH,
M_VMSGE, M_VMSGE,
M_NUM_MACROS M_NUM_MACROS
}; };

4
opcodes/riscv-opc.c
View File

@@ -1044,11 +1044,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, INSN_MACRO }, {"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, INSN_MACRO },
{"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS }, {"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS },
{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 }, {"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, NULL, INSN_MACRO }, {"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO },
{"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS }, {"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS },
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, NULL, INSN_MACRO }, {"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO },
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 }, {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 }, {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 }, {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },