[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.

VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.

opcodes	* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
	(print_insn_neon): Support disassembly of conditional
	instructions.

binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
	conditional VDUP instructions are disassembled correctly.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-cond.d.
	* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
	that VDUP instructions (which are conditional in A32) can be
	disassembled in thumb mode.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-thumb.d.

binutils/testsuite/binutils-all/arm/vdup-cond.d

@@ -0,0 +1,27 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle conditional neon (vdup) instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+:	0e800b10 	vdupeq.32	d0, r0
+[^:]+:	1e800b10 	vdupne.32	d0, r0
+[^:]+:	2e800b10 	vdupcs.32	d0, r0
+[^:]+:	3e800b10 	vdupcc.32	d0, r0
+[^:]+:	4e800b10 	vdupmi.32	d0, r0
+[^:]+:	5e800b10 	vduppl.32	d0, r0
+[^:]+:	6e800b10 	vdupvs.32	d0, r0
+[^:]+:	7e800b10 	vdupvc.32	d0, r0
+[^:]+:	8e800b10 	vduphi.32	d0, r0
+[^:]+:	9e800b10 	vdupls.32	d0, r0
+[^:]+:	ae800b10 	vdupge.32	d0, r0
+[^:]+:	be800b10 	vduplt.32	d0, r0
+[^:]+:	ce800b10 	vdupgt.32	d0, r0
+[^:]+:	de800b10 	vduple.32	d0, r0
+[^:]+:	ee800b10 	vdup.32	d0, r0

binutils/testsuite/binutils-all/arm/vdup-cond.s

@@ -0,0 +1,18 @@
+.text
+.arm
+.section .vdups, "ax"
+vdupeq.32  d0, r0
+vdupne.32  d0, r0
+vdupcs.32  d0, r0
+vdupcc.32  d0, r0
+vdupmi.32  d0, r0
+vduppl.32  d0, r0
+vdupvs.32  d0, r0
+vdupvc.32  d0, r0
+vduphi.32  d0, r0
+vdupls.32  d0, r0
+vdupge.32  d0, r0
+vduplt.32  d0, r0
+vdupgt.32  d0, r0
+vduple.32  d0, r0
+vdup.32    d0, r0

binutils/testsuite/binutils-all/arm/vdup-thumb.d

@@ -0,0 +1,13 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle vdup instructions in thumb
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+:	ee80 0b10 	vdup.32	d0, r0

binutils/testsuite/binutils-all/arm/vdup-thumb.s

@@ -0,0 +1,4 @@
+.text
+.thumb
+.section .vdups, "ax"
+vdup.32    d0, r0