forked from Imagelibrary/binutils-gdb
import gdb-2000-02-04 snapshot
This commit is contained in:
Jason Molenda
@@ -17,24 +17,24 @@
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#include "armdefs.h"
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extern unsigned ARMul_CoProInit(ARMul_State *state) ;
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extern void ARMul_CoProExit(ARMul_State *state) ;
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extern void ARMul_CoProAttach(ARMul_State *state, unsigned number,
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ARMul_CPInits *init, ARMul_CPExits *exit,
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ARMul_LDCs *ldc, ARMul_STCs *stc,
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ARMul_MRCs *mrc, ARMul_MCRs *mcr,
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ARMul_CDPs *cdp,
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ARMul_CPReads *read, ARMul_CPWrites *write) ;
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extern void ARMul_CoProDetach(ARMul_State *state, unsigned number) ;
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extern unsigned ARMul_CoProInit (ARMul_State * state);
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extern void ARMul_CoProExit (ARMul_State * state);
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extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
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ARMul_CPInits * init, ARMul_CPExits * exit,
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ARMul_LDCs * ldc, ARMul_STCs * stc,
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ARMul_MRCs * mrc, ARMul_MCRs * mcr,
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ARMul_CDPs * cdp,
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ARMul_CPReads * read, ARMul_CPWrites * write);
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extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
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/***************************************************************************\
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* Dummy Co-processors *
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\***************************************************************************/
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static unsigned NoCoPro3R(ARMul_State *state,unsigned,ARMword) ;
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static unsigned NoCoPro4R(ARMul_State *state,unsigned,ARMword,ARMword) ;
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static unsigned NoCoPro4W(ARMul_State *state,unsigned,ARMword,ARMword *) ;
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static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
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static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
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static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
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/***************************************************************************\
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* Define Co-Processor instruction handlers here *
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@@ -49,62 +49,72 @@ controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
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bit 6 controls late abort timimg and bit 7 controls big/little endian.
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*/
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static ARMword MMUReg[8] ;
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static ARMword MMUReg[8];
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static unsigned MMUInit(ARMul_State *state)
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{MMUReg[1] = state->prog32Sig << 4 |
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state->data32Sig << 5 |
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state->lateabtSig << 6 |
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state->bigendSig << 7 ;
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ARMul_ConsolePrint (state, ", MMU present") ;
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return(TRUE) ;
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static unsigned
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MMUInit (ARMul_State * state)
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{
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MMUReg[1] = state->prog32Sig << 4 |
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state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
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ARMul_ConsolePrint (state, ", MMU present");
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return (TRUE);
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}
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static unsigned MMUMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value)
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{int reg = BITS(16,19) & 7 ;
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static unsigned
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MMUMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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{
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int reg = BITS (16, 19) & 7;
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if (reg == 0)
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*value = 0x41440110 ;
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else
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*value = MMUReg[reg] ;
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return(ARMul_DONE) ;
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}
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if (reg == 0)
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*value = 0x41440110;
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else
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*value = MMUReg[reg];
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return (ARMul_DONE);
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}
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static unsigned MMUMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value)
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{int reg = BITS(16,19) & 7 ;
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static unsigned
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MMUMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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{
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int reg = BITS (16, 19) & 7;
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MMUReg[reg] = value ;
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if (reg == 1) {
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state->prog32Sig = value >> 4 & 1 ;
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state->data32Sig = value >> 5 & 1 ;
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state->lateabtSig = value >> 6 & 1 ;
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state->bigendSig = value >> 7 & 1 ;
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state->Emulate = TRUE ; /* force ARMulator to notice these now !*/
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MMUReg[reg] = value;
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if (reg == 1)
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{
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state->prog32Sig = value >> 4 & 1;
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state->data32Sig = value >> 5 & 1;
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state->lateabtSig = value >> 6 & 1;
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state->bigendSig = value >> 7 & 1;
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state->Emulate = TRUE; /* force ARMulator to notice these now ! */
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}
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return(ARMul_DONE) ;
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}
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return (ARMul_DONE);
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}
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static unsigned MMURead(ARMul_State *state, unsigned reg, ARMword *value)
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{if (reg == 0)
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*value = 0x41440110 ;
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else if (reg < 8)
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*value = MMUReg[reg] ;
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return(TRUE) ;
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}
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static unsigned
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MMURead (ARMul_State * state, unsigned reg, ARMword * value)
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{
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if (reg == 0)
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*value = 0x41440110;
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else if (reg < 8)
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*value = MMUReg[reg];
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return (TRUE);
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}
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static unsigned MMUWrite(ARMul_State *state, unsigned reg, ARMword value)
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{if (reg < 8)
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MMUReg[reg] = value ;
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if (reg == 1) {
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state->prog32Sig = value >> 4 & 1 ;
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state->data32Sig = value >> 5 & 1 ;
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state->lateabtSig = value >> 6 & 1 ;
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state->bigendSig = value >> 7 & 1 ;
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state->Emulate = TRUE ; /* force ARMulator to notice these now !*/
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static unsigned
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MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
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{
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if (reg < 8)
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MMUReg[reg] = value;
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if (reg == 1)
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{
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state->prog32Sig = value >> 4 & 1;
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state->data32Sig = value >> 5 & 1;
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state->lateabtSig = value >> 6 & 1;
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state->bigendSig = value >> 7 & 1;
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state->Emulate = TRUE; /* force ARMulator to notice these now ! */
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}
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return(TRUE) ;
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}
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return (TRUE);
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}
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/* What follows is the Validation Suite Coprocessor. It uses two
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@@ -118,240 +128,283 @@ way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
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bit time value in a CP register (actually it's the total number of N, S,
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I, C and F cyles) */
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static ARMword ValReg[16] ;
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static ARMword ValReg[16];
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static unsigned ValLDC(ARMul_State *state, unsigned type,
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ARMword instr, ARMword data)
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{static unsigned words ;
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if (type != ARMul_DATA) {
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words = 0 ;
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return(ARMul_DONE) ;
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}
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if (BIT(22)) { /* it's a long access, get two words */
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ValReg[BITS(12,15)] = data ;
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if (words++ == 4)
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return(ARMul_DONE) ;
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else
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return(ARMul_INC) ;
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}
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else { /* get just one word */
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ValReg[BITS(12,15)] = data ;
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return(ARMul_DONE) ;
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}
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}
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static unsigned ValSTC(ARMul_State *state, unsigned type,
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ARMword instr, ARMword *data)
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{static unsigned words ;
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if (type != ARMul_DATA) {
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words = 0 ;
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return(ARMul_DONE) ;
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}
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if (BIT(22)) { /* it's a long access, get two words */
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*data = ValReg[BITS(12,15)] ;
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if (words++ == 4)
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return(ARMul_DONE) ;
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else
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return(ARMul_INC) ;
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}
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else { /* get just one word */
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*data = ValReg[BITS(12,15)] ;
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return(ARMul_DONE) ;
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}
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}
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static unsigned ValMRC(ARMul_State *state, unsigned type, ARMword instr,ARMword *value)
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static unsigned
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ValLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
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{
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*value = ValReg[BITS(16,19)] ;
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return(ARMul_DONE) ;
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}
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static unsigned words;
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static unsigned ValMCR(ARMul_State *state, unsigned type, ARMword instr, ARMword value)
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{
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ValReg[BITS(16,19)] = value ;
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return(ARMul_DONE) ;
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}
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static unsigned ValCDP(ARMul_State *state, unsigned type, ARMword instr)
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{
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static unsigned long finish = 0 ;
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ARMword howlong ;
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howlong = ValReg[BITS(0,3)] ;
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if (BITS(20,23)==0) {
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if (type == ARMul_FIRST) { /* First cycle of a busy wait */
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finish = ARMul_Time(state) + howlong ;
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if (howlong == 0)
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return(ARMul_DONE) ;
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else
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return(ARMul_BUSY) ;
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}
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else if (type == ARMul_BUSY) {
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if (ARMul_Time(state) >= finish)
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return(ARMul_DONE) ;
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else
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return(ARMul_BUSY) ;
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}
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if (type != ARMul_DATA)
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{
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words = 0;
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return (ARMul_DONE);
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}
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if (BIT (22))
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{ /* it's a long access, get two words */
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ValReg[BITS (12, 15)] = data;
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if (words++ == 4)
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return (ARMul_DONE);
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else
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return (ARMul_INC);
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}
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else
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{ /* get just one word */
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ValReg[BITS (12, 15)] = data;
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return (ARMul_DONE);
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}
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return(ARMul_CANT) ;
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}
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static unsigned DoAFIQ(ARMul_State *state)
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{state->NfiqSig = LOW ;
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state->Exception++ ;
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return(0) ;
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}
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static unsigned DoAIRQ(ARMul_State *state)
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{state->NirqSig = LOW ;
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state->Exception++ ;
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return(0) ;
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static unsigned
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ValSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
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{
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static unsigned words;
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if (type != ARMul_DATA)
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{
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words = 0;
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return (ARMul_DONE);
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}
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if (BIT (22))
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{ /* it's a long access, get two words */
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*data = ValReg[BITS (12, 15)];
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if (words++ == 4)
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return (ARMul_DONE);
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else
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return (ARMul_INC);
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}
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else
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{ /* get just one word */
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*data = ValReg[BITS (12, 15)];
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return (ARMul_DONE);
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}
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}
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static unsigned IntCDP(ARMul_State *state, unsigned type, ARMword instr)
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{static unsigned long finish ;
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ARMword howlong ;
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static unsigned
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ValMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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{
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*value = ValReg[BITS (16, 19)];
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return (ARMul_DONE);
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}
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howlong = ValReg[BITS(0,3)] ;
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switch((int)BITS(20,23)) {
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case 0 : if (type == ARMul_FIRST) { /* First cycle of a busy wait */
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finish = ARMul_Time(state) + howlong ;
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if (howlong == 0)
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return(ARMul_DONE) ;
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else
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return(ARMul_BUSY) ;
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}
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else if (type == ARMul_BUSY) {
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if (ARMul_Time(state) >= finish)
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return(ARMul_DONE) ;
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else
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return(ARMul_BUSY) ;
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}
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return(ARMul_DONE) ;
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case 1 : if (howlong == 0)
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ARMul_Abort(state,ARMul_FIQV) ;
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else
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ARMul_ScheduleEvent(state,howlong,DoAFIQ) ;
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return(ARMul_DONE) ;
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case 2 : if (howlong == 0)
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ARMul_Abort(state,ARMul_IRQV) ;
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else
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ARMul_ScheduleEvent(state,howlong,DoAIRQ) ;
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return(ARMul_DONE) ;
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case 3 : state->NfiqSig = HIGH ;
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state->Exception-- ;
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return(ARMul_DONE) ;
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case 4 : state->NirqSig = HIGH ;
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state->Exception-- ;
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return(ARMul_DONE) ;
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case 5 : ValReg[BITS(0,3)] = ARMul_Time(state) ;
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return(ARMul_DONE) ;
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static unsigned
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ValMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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{
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ValReg[BITS (16, 19)] = value;
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return (ARMul_DONE);
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}
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static unsigned
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ValCDP (ARMul_State * state, unsigned type, ARMword instr)
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{
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static unsigned long finish = 0;
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ARMword howlong;
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howlong = ValReg[BITS (0, 3)];
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if (BITS (20, 23) == 0)
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{
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if (type == ARMul_FIRST)
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{ /* First cycle of a busy wait */
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finish = ARMul_Time (state) + howlong;
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if (howlong == 0)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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else if (type == ARMul_BUSY)
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{
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if (ARMul_Time (state) >= finish)
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return (ARMul_DONE);
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else
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return (ARMul_BUSY);
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}
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}
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return(ARMul_CANT) ;
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}
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return (ARMul_CANT);
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}
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static unsigned
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DoAFIQ (ARMul_State * state)
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{
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state->NfiqSig = LOW;
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state->Exception++;
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return (0);
|
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}
|
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static unsigned
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DoAIRQ (ARMul_State * state)
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{
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state->NirqSig = LOW;
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state->Exception++;
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return (0);
|
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}
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static unsigned
|
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IntCDP (ARMul_State * state, unsigned type, ARMword instr)
|
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{
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static unsigned long finish;
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ARMword howlong;
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howlong = ValReg[BITS (0, 3)];
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switch ((int) BITS (20, 23))
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{
|
||||
case 0:
|
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if (type == ARMul_FIRST)
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{ /* First cycle of a busy wait */
|
||||
finish = ARMul_Time (state) + howlong;
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if (howlong == 0)
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return (ARMul_DONE);
|
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else
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return (ARMul_BUSY);
|
||||
}
|
||||
else if (type == ARMul_BUSY)
|
||||
{
|
||||
if (ARMul_Time (state) >= finish)
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||||
return (ARMul_DONE);
|
||||
else
|
||||
return (ARMul_BUSY);
|
||||
}
|
||||
return (ARMul_DONE);
|
||||
case 1:
|
||||
if (howlong == 0)
|
||||
ARMul_Abort (state, ARMul_FIQV);
|
||||
else
|
||||
ARMul_ScheduleEvent (state, howlong, DoAFIQ);
|
||||
return (ARMul_DONE);
|
||||
case 2:
|
||||
if (howlong == 0)
|
||||
ARMul_Abort (state, ARMul_IRQV);
|
||||
else
|
||||
ARMul_ScheduleEvent (state, howlong, DoAIRQ);
|
||||
return (ARMul_DONE);
|
||||
case 3:
|
||||
state->NfiqSig = HIGH;
|
||||
state->Exception--;
|
||||
return (ARMul_DONE);
|
||||
case 4:
|
||||
state->NirqSig = HIGH;
|
||||
state->Exception--;
|
||||
return (ARMul_DONE);
|
||||
case 5:
|
||||
ValReg[BITS (0, 3)] = ARMul_Time (state);
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return (ARMul_DONE);
|
||||
}
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||||
return (ARMul_CANT);
|
||||
}
|
||||
|
||||
/***************************************************************************\
|
||||
* Install co-processor instruction handlers in this routine *
|
||||
\***************************************************************************/
|
||||
|
||||
unsigned ARMul_CoProInit(ARMul_State *state)
|
||||
{register unsigned i ;
|
||||
unsigned
|
||||
ARMul_CoProInit (ARMul_State * state)
|
||||
{
|
||||
register unsigned i;
|
||||
|
||||
for (i = 0 ; i < 16 ; i++) /* initialise tham all first */
|
||||
ARMul_CoProDetach(state, i) ;
|
||||
for (i = 0; i < 16; i++) /* initialise tham all first */
|
||||
ARMul_CoProDetach (state, i);
|
||||
|
||||
/* Install CoPro Instruction handlers here
|
||||
The format is
|
||||
ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
|
||||
LDC routine, STC routine, MRC routine, MCR routine,
|
||||
CDP routine, Read Reg routine, Write Reg routine) ;
|
||||
/* Install CoPro Instruction handlers here
|
||||
The format is
|
||||
ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
|
||||
LDC routine, STC routine, MRC routine, MCR routine,
|
||||
CDP routine, Read Reg routine, Write Reg routine) ;
|
||||
*/
|
||||
|
||||
ARMul_CoProAttach(state, 4, NULL, NULL,
|
||||
ValLDC, ValSTC, ValMRC, ValMCR,
|
||||
ValCDP, NULL, NULL) ;
|
||||
ARMul_CoProAttach (state, 4, NULL, NULL,
|
||||
ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
|
||||
|
||||
ARMul_CoProAttach(state, 5, NULL, NULL,
|
||||
NULL, NULL, ValMRC, ValMCR,
|
||||
IntCDP, NULL, NULL) ;
|
||||
ARMul_CoProAttach (state, 5, NULL, NULL,
|
||||
NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
|
||||
|
||||
ARMul_CoProAttach(state, 15, MMUInit, NULL,
|
||||
NULL, NULL, MMUMRC, MMUMCR,
|
||||
NULL, MMURead, MMUWrite) ;
|
||||
ARMul_CoProAttach (state, 15, MMUInit, NULL,
|
||||
NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
|
||||
|
||||
|
||||
/* No handlers below here */
|
||||
/* No handlers below here */
|
||||
|
||||
for (i = 0 ; i < 16 ; i++) /* Call all the initialisation routines */
|
||||
if (state->CPInit[i])
|
||||
(state->CPInit[i])(state) ;
|
||||
return(TRUE) ;
|
||||
}
|
||||
for (i = 0; i < 16; i++) /* Call all the initialisation routines */
|
||||
if (state->CPInit[i])
|
||||
(state->CPInit[i]) (state);
|
||||
return (TRUE);
|
||||
}
|
||||
|
||||
/***************************************************************************\
|
||||
* Install co-processor finalisation routines in this routine *
|
||||
\***************************************************************************/
|
||||
|
||||
void ARMul_CoProExit(ARMul_State *state)
|
||||
{register unsigned i ;
|
||||
void
|
||||
ARMul_CoProExit (ARMul_State * state)
|
||||
{
|
||||
register unsigned i;
|
||||
|
||||
for (i = 0 ; i < 16 ; i++)
|
||||
for (i = 0; i < 16; i++)
|
||||
if (state->CPExit[i])
|
||||
(state->CPExit[i])(state) ;
|
||||
for (i = 0 ; i < 16 ; i++) /* Detach all handlers */
|
||||
ARMul_CoProDetach(state, i) ;
|
||||
}
|
||||
(state->CPExit[i]) (state);
|
||||
for (i = 0; i < 16; i++) /* Detach all handlers */
|
||||
ARMul_CoProDetach (state, i);
|
||||
}
|
||||
|
||||
/***************************************************************************\
|
||||
* Routines to hook Co-processors into ARMulator *
|
||||
\***************************************************************************/
|
||||
|
||||
void ARMul_CoProAttach(ARMul_State *state, unsigned number,
|
||||
ARMul_CPInits *init, ARMul_CPExits *exit,
|
||||
ARMul_LDCs *ldc, ARMul_STCs *stc,
|
||||
ARMul_MRCs *mrc, ARMul_MCRs *mcr, ARMul_CDPs *cdp,
|
||||
ARMul_CPReads *read, ARMul_CPWrites *write)
|
||||
{if (init != NULL)
|
||||
state->CPInit[number] = init ;
|
||||
if (exit != NULL)
|
||||
state->CPExit[number] = exit ;
|
||||
if (ldc != NULL)
|
||||
state->LDC[number] = ldc ;
|
||||
if (stc != NULL)
|
||||
state->STC[number] = stc ;
|
||||
if (mrc != NULL)
|
||||
state->MRC[number] = mrc ;
|
||||
if (mcr != NULL)
|
||||
state->MCR[number] = mcr ;
|
||||
if (cdp != NULL)
|
||||
state->CDP[number] = cdp ;
|
||||
if (read != NULL)
|
||||
state->CPRead[number] = read ;
|
||||
if (write != NULL)
|
||||
state->CPWrite[number] = write ;
|
||||
void
|
||||
ARMul_CoProAttach (ARMul_State * state, unsigned number,
|
||||
ARMul_CPInits * init, ARMul_CPExits * exit,
|
||||
ARMul_LDCs * ldc, ARMul_STCs * stc,
|
||||
ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
|
||||
ARMul_CPReads * read, ARMul_CPWrites * write)
|
||||
{
|
||||
if (init != NULL)
|
||||
state->CPInit[number] = init;
|
||||
if (exit != NULL)
|
||||
state->CPExit[number] = exit;
|
||||
if (ldc != NULL)
|
||||
state->LDC[number] = ldc;
|
||||
if (stc != NULL)
|
||||
state->STC[number] = stc;
|
||||
if (mrc != NULL)
|
||||
state->MRC[number] = mrc;
|
||||
if (mcr != NULL)
|
||||
state->MCR[number] = mcr;
|
||||
if (cdp != NULL)
|
||||
state->CDP[number] = cdp;
|
||||
if (read != NULL)
|
||||
state->CPRead[number] = read;
|
||||
if (write != NULL)
|
||||
state->CPWrite[number] = write;
|
||||
}
|
||||
|
||||
void ARMul_CoProDetach(ARMul_State *state, unsigned number)
|
||||
{ARMul_CoProAttach(state, number, NULL, NULL,
|
||||
NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
|
||||
NoCoPro3R, NULL, NULL) ;
|
||||
state->CPInit[number] = NULL ;
|
||||
state->CPExit[number] = NULL ;
|
||||
state->CPRead[number] = NULL ;
|
||||
state->CPWrite[number] = NULL ;
|
||||
void
|
||||
ARMul_CoProDetach (ARMul_State * state, unsigned number)
|
||||
{
|
||||
ARMul_CoProAttach (state, number, NULL, NULL,
|
||||
NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
|
||||
NoCoPro3R, NULL, NULL);
|
||||
state->CPInit[number] = NULL;
|
||||
state->CPExit[number] = NULL;
|
||||
state->CPRead[number] = NULL;
|
||||
state->CPWrite[number] = NULL;
|
||||
}
|
||||
|
||||
/***************************************************************************\
|
||||
* There is no CoPro around, so Undefined Instruction trap *
|
||||
\***************************************************************************/
|
||||
|
||||
static unsigned NoCoPro3R(ARMul_State *state,unsigned a,ARMword b)
|
||||
{return(ARMul_CANT) ;}
|
||||
static unsigned
|
||||
NoCoPro3R (ARMul_State * state, unsigned a, ARMword b)
|
||||
{
|
||||
return (ARMul_CANT);
|
||||
}
|
||||
|
||||
static unsigned NoCoPro4R(ARMul_State *state, unsigned a,ARMword b,ARMword c)
|
||||
{return(ARMul_CANT) ;}
|
||||
static unsigned
|
||||
NoCoPro4R (ARMul_State * state, unsigned a, ARMword b, ARMword c)
|
||||
{
|
||||
return (ARMul_CANT);
|
||||
}
|
||||
|
||||
static unsigned NoCoPro4W(ARMul_State *state, unsigned a,ARMword b,ARMword *c)
|
||||
{return(ARMul_CANT) ;}
|
||||
static unsigned
|
||||
NoCoPro4W (ARMul_State * state, unsigned a, ARMword b, ARMword * c)
|
||||
{
|
||||
return (ARMul_CANT);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user