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[AArch64] Add ARMv8.2 instructions BFC and REV64.

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ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.

This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/alias-2.d: New.
	* gas/aarch64/alias-2.s: New.

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_op): Add OP_BFC.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-asm.c (convert_bfc_to_bfm): New.
	(convert_to_real): Add case for OP_BFC.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c: (convert_bfm_to_bfc): New.
	(convert_to_alias): Add case for OP_BFC.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
	to allow width operand in three-operand instructions.
	* aarch64-tbl.h (QL_BF1): New.
	(aarch64_feature_v8_2): New.
	(ARMV8_2): New.
	(aarch64_opcode_table): Add "bfc".

Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
This commit is contained in:
Matthew Wahab
2015-11-27 15:25:08 +00:00
parent e19616610d
commit d685192a58
13 changed files with 1106 additions and 861 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/testsuite/ChangeLog
View File

@@ -1,3 +1,8 @@
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/alias-2.d: New.
* gas/aarch64/alias-2.s: New.
2015-11-27 Matthew Wahab <matthew.wahab@arm.com> 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: New. * gas/aarch64/sysreg-2.d: New.

98
gas/testsuite/gas/aarch64/alias-2.d Normal file
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@@ -0,0 +1,98 @@
#objdump: -dr
#as: -march=armv8.2-a
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
[0-9a-f]+: b34107e0 bfxil x0, xzr, #1, #1
[0-9a-f]+: b3410420 bfxil x0, x1, #1, #1
[0-9a-f]+: b341043f bfxil xzr, x1, #1, #1
[0-9a-f]+: b34107ff bfxil xzr, xzr, #1, #1
[0-9a-f]+: b34123e0 bfxil x0, xzr, #1, #8
[0-9a-f]+: b3412020 bfxil x0, x1, #1, #8
[0-9a-f]+: b341203f bfxil xzr, x1, #1, #8
[0-9a-f]+: b34123ff bfxil xzr, xzr, #1, #8
[0-9a-f]+: b3413fe0 bfxil x0, xzr, #1, #15
[0-9a-f]+: b3413c20 bfxil x0, x1, #1, #15
[0-9a-f]+: b3413c3f bfxil xzr, x1, #1, #15
[0-9a-f]+: b3413fff bfxil xzr, xzr, #1, #15
[0-9a-f]+: b35007e0 bfc x0, #48, #2
[0-9a-f]+: b3500420 bfi x0, x1, #48, #2
[0-9a-f]+: b350043f bfi xzr, x1, #48, #2
[0-9a-f]+: b35007ff bfc xzr, #48, #2
[0-9a-f]+: b35023e0 bfc x0, #48, #9
[0-9a-f]+: b3502020 bfi x0, x1, #48, #9
[0-9a-f]+: b350203f bfi xzr, x1, #48, #9
[0-9a-f]+: b35023ff bfc xzr, #48, #9
[0-9a-f]+: b3503fe0 bfc x0, #48, #16
[0-9a-f]+: b3503c20 bfi x0, x1, #48, #16
[0-9a-f]+: b3503c3f bfi xzr, x1, #48, #16
[0-9a-f]+: b3503fff bfc xzr, #48, #16
[0-9a-f]+: b35f07e0 bfc x0, #33, #2
[0-9a-f]+: b35f0420 bfi x0, x1, #33, #2
[0-9a-f]+: b35f043f bfi xzr, x1, #33, #2
[0-9a-f]+: b35f07ff bfc xzr, #33, #2
[0-9a-f]+: b35f23e0 bfc x0, #33, #9
[0-9a-f]+: b35f2020 bfi x0, x1, #33, #9
[0-9a-f]+: b35f203f bfi xzr, x1, #33, #9
[0-9a-f]+: b35f23ff bfc xzr, #33, #9
[0-9a-f]+: b35f3fe0 bfc x0, #33, #16
[0-9a-f]+: b35f3c20 bfi x0, x1, #33, #16
[0-9a-f]+: b35f3c3f bfi xzr, x1, #33, #16
[0-9a-f]+: b35f3fff bfc xzr, #33, #16
[0-9a-f]+: b37f03e0 bfc x0, #1, #1
[0-9a-f]+: b37f0020 bfi x0, x1, #1, #1
[0-9a-f]+: b37f003f bfi xzr, x1, #1, #1
[0-9a-f]+: b37f03ff bfc xzr, #1, #1
[0-9a-f]+: b37f1fe0 bfc x0, #1, #8
[0-9a-f]+: b37f1c20 bfi x0, x1, #1, #8
[0-9a-f]+: b37f1c3f bfi xzr, x1, #1, #8
[0-9a-f]+: b37f1fff bfc xzr, #1, #8
[0-9a-f]+: b37f3be0 bfc x0, #1, #15
[0-9a-f]+: b37f3820 bfi x0, x1, #1, #15
[0-9a-f]+: b37f383f bfi xzr, x1, #1, #15
[0-9a-f]+: b37f3bff bfc xzr, #1, #15
[0-9a-f]+: b37003e0 bfc x0, #16, #1
[0-9a-f]+: b3700020 bfi x0, x1, #16, #1
[0-9a-f]+: b370003f bfi xzr, x1, #16, #1
[0-9a-f]+: b37003ff bfc xzr, #16, #1
[0-9a-f]+: b3701fe0 bfc x0, #16, #8
[0-9a-f]+: b3701c20 bfi x0, x1, #16, #8
[0-9a-f]+: b3701c3f bfi xzr, x1, #16, #8
[0-9a-f]+: b3701fff bfc xzr, #16, #8
[0-9a-f]+: b3703be0 bfc x0, #16, #15
[0-9a-f]+: b3703820 bfi x0, x1, #16, #15
[0-9a-f]+: b370383f bfi xzr, x1, #16, #15
[0-9a-f]+: b3703bff bfc xzr, #16, #15
[0-9a-f]+: b36103e0 bfc x0, #31, #1
[0-9a-f]+: b3610020 bfi x0, x1, #31, #1
[0-9a-f]+: b361003f bfi xzr, x1, #31, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3611fe0 bfc x0, #31, #8
[0-9a-f]+: b3611c20 bfi x0, x1, #31, #8
[0-9a-f]+: b3611c3f bfi xzr, x1, #31, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3613be0 bfc x0, #31, #15
[0-9a-f]+: b3613820 bfi x0, x1, #31, #15
[0-9a-f]+: b361383f bfi xzr, x1, #31, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15

31
gas/testsuite/gas/aarch64/alias-2.s Normal file
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@@ -0,0 +1,31 @@
/* alias-2.s Test file for ARMv8.2 AArch64 instructions aliases or disassembly
preference. */
/* <bfm> [Xd|xzr], [xzr|<Xr>], <imm>, <width> */
.macro bfm_inst op imm width
\op x0, xzr, #\imm, #\width
\op x0, x1, #\imm, #\width
\op xzr, x1, #\imm, #\width
\op xzr, xzr, #\imm, #\width
.endm
/* bfc [Xd|xzr], <imm>, <width> */
.macro bfc_inst imm width
bfc x0, #\imm, #\width
bfc xzr, #\imm, #\width
.endm
.text
.irp op, bfm, bfi
.irp imm, 1, 16, 31
.irp width, 1, 8, 15
bfm_inst \op, \imm, \width
.endr
.endr
.endr
.irp imm, 1, 16, 31
.irp width, 1, 8, 15
bfc_inst \imm, \width
.endr
.endr

4
include/opcode/ChangeLog
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@@ -1,3 +1,7 @@
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_op): Add OP_BFC.
2015-11-27 Matthew Wahab <matthew.wahab@arm.com> 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): New. * aarch64.h (AARCH64_FEATURE_F16): New.

1
include/opcode/aarch64.h
View File

@@ -438,6 +438,7 @@ enum aarch64_op
OP_SBFX, OP_SBFX,
OP_SBFIZ, OP_SBFIZ,
OP_BFI, OP_BFI,
OP_BFC, /* ARMv8.2. */
OP_UBFIZ, OP_UBFIZ,
OP_UXTB, OP_UXTB,
OP_UXTH, OP_UXTH,

16
opcodes/ChangeLog
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@@ -1,3 +1,19 @@
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-asm.c (convert_bfc_to_bfm): New.
(convert_to_real): Add case for OP_BFC.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c: (convert_bfm_to_bfc): New.
(convert_to_alias): Add case for OP_BFC.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
to allow width operand in three-operand instructions.
* aarch64-tbl.h (QL_BF1): New.
(aarch64_feature_v8_2): New.
(ARMV8_2): New.
(aarch64_opcode_table): Add "bfc".
2015-11-27 Matthew Wahab <matthew.wahab@arm.com> 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate. * aarch64-asm-2.c: Regenerate.

571
opcodes/aarch64-asm-2.c
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@@ -120,318 +120,319 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 501: /* sbfm */ case 501: /* sbfm */
value = 501; /* --> sbfm. */ value = 501; /* --> sbfm. */
break; break;
case 510: /* bfxil */ case 510: /* bfc */
case 511: /* bfxil */
case 509: /* bfi */ case 509: /* bfi */
case 508: /* bfm */ case 508: /* bfm */
value = 508; /* --> bfm. */ value = 508; /* --> bfm. */
break; break;
case 515: /* uxth */ case 516: /* uxth */
case 514: /* uxtb */ case 515: /* uxtb */
case 517: /* lsr */ case 518: /* lsr */
case 516: /* lsl */ case 517: /* lsl */
case 513: /* ubfx */ case 514: /* ubfx */
case 512: /* ubfiz */ case 513: /* ubfiz */
case 511: /* ubfm */ case 512: /* ubfm */
value = 511; /* --> ubfm. */ value = 512; /* --> ubfm. */
break; break;
case 535: /* cset */ case 536: /* cset */
case 534: /* cinc */ case 535: /* cinc */
case 533: /* csinc */ case 534: /* csinc */
value = 533; /* --> csinc. */ value = 534; /* --> csinc. */
break; break;
case 538: /* csetm */ case 539: /* csetm */
case 537: /* cinv */ case 538: /* cinv */
case 536: /* csinv */ case 537: /* csinv */
value = 536; /* --> csinv. */ value = 537; /* --> csinv. */
break; break;
case 540: /* cneg */ case 541: /* cneg */
case 539: /* csneg */ case 540: /* csneg */
value = 539; /* --> csneg. */ value = 540; /* --> csneg. */
break; break;
case 565: /* lsl */ case 566: /* lsl */
case 564: /* lslv */ case 565: /* lslv */
value = 564; /* --> lslv. */ value = 565; /* --> lslv. */
break; break;
case 567: /* lsr */ case 568: /* lsr */
case 566: /* lsrv */ case 567: /* lsrv */
value = 566; /* --> lsrv. */ value = 567; /* --> lsrv. */
break; break;
case 569: /* asr */ case 570: /* asr */
case 568: /* asrv */ case 569: /* asrv */
value = 568; /* --> asrv. */ value = 569; /* --> asrv. */
break; break;
case 571: /* ror */ case 572: /* ror */
case 570: /* rorv */ case 571: /* rorv */
value = 570; /* --> rorv. */ value = 571; /* --> rorv. */
break; break;
case 581: /* mul */ case 582: /* mul */
case 580: /* madd */ case 581: /* madd */
value = 580; /* --> madd. */ value = 581; /* --> madd. */
break; break;
case 583: /* mneg */ case 584: /* mneg */
case 582: /* msub */ case 583: /* msub */
value = 582; /* --> msub. */ value = 583; /* --> msub. */
break; break;
case 585: /* smull */ case 586: /* smull */
case 584: /* smaddl */ case 585: /* smaddl */
value = 584; /* --> smaddl. */ value = 585; /* --> smaddl. */
break; break;
case 587: /* smnegl */ case 588: /* smnegl */
case 586: /* smsubl */ case 587: /* smsubl */
value = 586; /* --> smsubl. */ value = 587; /* --> smsubl. */
break; break;
case 590: /* umull */ case 591: /* umull */
case 589: /* umaddl */ case 590: /* umaddl */
value = 589; /* --> umaddl. */ value = 590; /* --> umaddl. */
break; break;
case 592: /* umnegl */ case 593: /* umnegl */
case 591: /* umsubl */ case 592: /* umsubl */
value = 591; /* --> umsubl. */ value = 592; /* --> umsubl. */
break; break;
case 603: /* ror */ case 604: /* ror */
case 602: /* extr */ case 603: /* extr */
value = 602; /* --> extr. */ value = 603; /* --> extr. */
break; break;
case 760: /* bic */ case 761: /* bic */
case 759: /* and */ case 760: /* and */
value = 759; /* --> and. */ value = 760; /* --> and. */
break; break;
case 762: /* mov */ case 763: /* mov */
case 761: /* orr */ case 762: /* orr */
value = 761; /* --> orr. */ value = 762; /* --> orr. */
break; break;
case 765: /* tst */ case 766: /* tst */
case 764: /* ands */ case 765: /* ands */
value = 764; /* --> ands. */ value = 765; /* --> ands. */
break; break;
case 770: /* uxtw */ case 771: /* uxtw */
case 769: /* mov */ case 770: /* mov */
case 768: /* orr */ case 769: /* orr */
value = 768; /* --> orr. */ value = 769; /* --> orr. */
break; break;
case 772: /* mvn */ case 773: /* mvn */
case 771: /* orn */ case 772: /* orn */
value = 771; /* --> orn. */ value = 772; /* --> orn. */
break; break;
case 776: /* tst */ case 777: /* tst */
case 775: /* ands */ case 776: /* ands */
value = 775; /* --> ands. */ value = 776; /* --> ands. */
break; break;
case 902: /* staddb */ case 903: /* staddb */
case 806: /* ldaddb */ case 807: /* ldaddb */
value = 806; /* --> ldaddb. */ value = 807; /* --> ldaddb. */
break; break;
case 903: /* staddh */ case 904: /* staddh */
case 807: /* ldaddh */ case 808: /* ldaddh */
value = 807; /* --> ldaddh. */ value = 808; /* --> ldaddh. */
break; break;
case 904: /* stadd */ case 905: /* stadd */
case 808: /* ldadd */ case 809: /* ldadd */
value = 808; /* --> ldadd. */ value = 809; /* --> ldadd. */
break; break;
case 905: /* staddlb */ case 906: /* staddlb */
case 810: /* ldaddlb */ case 811: /* ldaddlb */
value = 810; /* --> ldaddlb. */ value = 811; /* --> ldaddlb. */
break; break;
case 906: /* staddlh */ case 907: /* staddlh */
case 813: /* ldaddlh */ case 814: /* ldaddlh */
value = 813; /* --> ldaddlh. */ value = 814; /* --> ldaddlh. */
break; break;
case 907: /* staddl */ case 908: /* staddl */
case 816: /* ldaddl */ case 817: /* ldaddl */
value = 816; /* --> ldaddl. */ value = 817; /* --> ldaddl. */
break; break;
case 908: /* stclrb */ case 909: /* stclrb */
case 818: /* ldclrb */ case 819: /* ldclrb */
value = 818; /* --> ldclrb. */ value = 819; /* --> ldclrb. */
break; break;
case 909: /* stclrh */ case 910: /* stclrh */
case 819: /* ldclrh */ case 820: /* ldclrh */
value = 819; /* --> ldclrh. */ value = 820; /* --> ldclrh. */
break; break;
case 910: /* stclr */ case 911: /* stclr */
case 820: /* ldclr */ case 821: /* ldclr */
value = 820; /* --> ldclr. */ value = 821; /* --> ldclr. */
break; break;
case 911: /* stclrlb */ case 912: /* stclrlb */
case 822: /* ldclrlb */ case 823: /* ldclrlb */
value = 822; /* --> ldclrlb. */ value = 823; /* --> ldclrlb. */
break; break;
case 912: /* stclrlh */ case 913: /* stclrlh */
case 825: /* ldclrlh */ case 826: /* ldclrlh */
value = 825; /* --> ldclrlh. */ value = 826; /* --> ldclrlh. */
break; break;
case 913: /* stclrl */ case 914: /* stclrl */
case 828: /* ldclrl */ case 829: /* ldclrl */
value = 828; /* --> ldclrl. */ value = 829; /* --> ldclrl. */
break; break;
case 914: /* steorb */ case 915: /* steorb */
case 830: /* ldeorb */ case 831: /* ldeorb */
value = 830; /* --> ldeorb. */ value = 831; /* --> ldeorb. */
break; break;
case 915: /* steorh */ case 916: /* steorh */
case 831: /* ldeorh */ case 832: /* ldeorh */
value = 831; /* --> ldeorh. */ value = 832; /* --> ldeorh. */
break; break;
case 916: /* steor */ case 917: /* steor */
case 832: /* ldeor */ case 833: /* ldeor */
value = 832; /* --> ldeor. */ value = 833; /* --> ldeor. */
break; break;
case 917: /* steorlb */ case 918: /* steorlb */
case 834: /* ldeorlb */ case 835: /* ldeorlb */
value = 834; /* --> ldeorlb. */ value = 835; /* --> ldeorlb. */
break; break;
case 918: /* steorlh */ case 919: /* steorlh */
case 837: /* ldeorlh */ case 838: /* ldeorlh */
value = 837; /* --> ldeorlh. */ value = 838; /* --> ldeorlh. */
break; break;
case 919: /* steorl */ case 920: /* steorl */
case 840: /* ldeorl */ case 841: /* ldeorl */
value = 840; /* --> ldeorl. */ value = 841; /* --> ldeorl. */
break; break;
case 920: /* stsetb */ case 921: /* stsetb */
case 842: /* ldsetb */ case 843: /* ldsetb */
value = 842; /* --> ldsetb. */ value = 843; /* --> ldsetb. */
break; break;
case 921: /* stseth */ case 922: /* stseth */
case 843: /* ldseth */ case 844: /* ldseth */
value = 843; /* --> ldseth. */ value = 844; /* --> ldseth. */
break; break;
case 922: /* stset */ case 923: /* stset */
case 844: /* ldset */ case 845: /* ldset */
value = 844; /* --> ldset. */ value = 845; /* --> ldset. */
break; break;
case 923: /* stsetlb */ case 924: /* stsetlb */
case 846: /* ldsetlb */ case 847: /* ldsetlb */
value = 846; /* --> ldsetlb. */ value = 847; /* --> ldsetlb. */
break; break;
case 924: /* stsetlh */ case 925: /* stsetlh */
case 849: /* ldsetlh */ case 850: /* ldsetlh */
value = 849; /* --> ldsetlh. */ value = 850; /* --> ldsetlh. */
break; break;
case 925: /* stsetl */ case 926: /* stsetl */
case 852: /* ldsetl */ case 853: /* ldsetl */
value = 852; /* --> ldsetl. */ value = 853; /* --> ldsetl. */
break; break;
case 926: /* stsmaxb */ case 927: /* stsmaxb */
case 854: /* ldsmaxb */ case 855: /* ldsmaxb */
value = 854; /* --> ldsmaxb. */ value = 855; /* --> ldsmaxb. */
break; break;
case 927: /* stsmaxh */ case 928: /* stsmaxh */
case 855: /* ldsmaxh */ case 856: /* ldsmaxh */
value = 855; /* --> ldsmaxh. */ value = 856; /* --> ldsmaxh. */
break; break;
case 928: /* stsmax */ case 929: /* stsmax */
case 856: /* ldsmax */ case 857: /* ldsmax */
value = 856; /* --> ldsmax. */ value = 857; /* --> ldsmax. */
break; break;
case 929: /* stsmaxlb */ case 930: /* stsmaxlb */
case 858: /* ldsmaxlb */ case 859: /* ldsmaxlb */
value = 858; /* --> ldsmaxlb. */ value = 859; /* --> ldsmaxlb. */
break; break;
case 930: /* stsmaxlh */ case 931: /* stsmaxlh */
case 861: /* ldsmaxlh */ case 862: /* ldsmaxlh */
value = 861; /* --> ldsmaxlh. */ value = 862; /* --> ldsmaxlh. */
break; break;
case 931: /* stsmaxl */ case 932: /* stsmaxl */
case 864: /* ldsmaxl */ case 865: /* ldsmaxl */
value = 864; /* --> ldsmaxl. */ value = 865; /* --> ldsmaxl. */
break; break;
case 932: /* stsminb */ case 933: /* stsminb */
case 866: /* ldsminb */ case 867: /* ldsminb */
value = 866; /* --> ldsminb. */ value = 867; /* --> ldsminb. */
break; break;
case 933: /* stsminh */ case 934: /* stsminh */
case 867: /* ldsminh */ case 868: /* ldsminh */
value = 867; /* --> ldsminh. */ value = 868; /* --> ldsminh. */
break; break;
case 934: /* stsmin */ case 935: /* stsmin */
case 868: /* ldsmin */ case 869: /* ldsmin */
value = 868; /* --> ldsmin. */ value = 869; /* --> ldsmin. */
break; break;
case 935: /* stsminlb */ case 936: /* stsminlb */
case 870: /* ldsminlb */ case 871: /* ldsminlb */
value = 870; /* --> ldsminlb. */ value = 871; /* --> ldsminlb. */
break; break;
case 936: /* stsminlh */ case 937: /* stsminlh */
case 873: /* ldsminlh */ case 874: /* ldsminlh */
value = 873; /* --> ldsminlh. */ value = 874; /* --> ldsminlh. */
break; break;
case 937: /* stsminl */ case 938: /* stsminl */
case 876: /* ldsminl */ case 877: /* ldsminl */
value = 876; /* --> ldsminl. */ value = 877; /* --> ldsminl. */
break; break;
case 938: /* stumaxb */ case 939: /* stumaxb */
case 878: /* ldumaxb */ case 879: /* ldumaxb */
value = 878; /* --> ldumaxb. */ value = 879; /* --> ldumaxb. */
break; break;
case 939: /* stumaxh */ case 940: /* stumaxh */
case 879: /* ldumaxh */ case 880: /* ldumaxh */
value = 879; /* --> ldumaxh. */ value = 880; /* --> ldumaxh. */
break; break;
case 940: /* stumax */ case 941: /* stumax */
case 880: /* ldumax */ case 881: /* ldumax */
value = 880; /* --> ldumax. */ value = 881; /* --> ldumax. */
break; break;
case 941: /* stumaxlb */ case 942: /* stumaxlb */
case 882: /* ldumaxlb */ case 883: /* ldumaxlb */
value = 882; /* --> ldumaxlb. */ value = 883; /* --> ldumaxlb. */
break; break;
case 942: /* stumaxlh */ case 943: /* stumaxlh */
case 885: /* ldumaxlh */ case 886: /* ldumaxlh */
value = 885; /* --> ldumaxlh. */ value = 886; /* --> ldumaxlh. */
break; break;
case 943: /* stumaxl */ case 944: /* stumaxl */
case 888: /* ldumaxl */ case 889: /* ldumaxl */
value = 888; /* --> ldumaxl. */ value = 889; /* --> ldumaxl. */
break; break;
case 944: /* stuminb */ case 945: /* stuminb */
case 890: /* lduminb */ case 891: /* lduminb */
value = 890; /* --> lduminb. */ value = 891; /* --> lduminb. */
break; break;
case 945: /* stuminh */ case 946: /* stuminh */
case 891: /* lduminh */ case 892: /* lduminh */
value = 891; /* --> lduminh. */ value = 892; /* --> lduminh. */
break; break;
case 946: /* stumin */ case 947: /* stumin */
case 892: /* ldumin */ case 893: /* ldumin */
value = 892; /* --> ldumin. */ value = 893; /* --> ldumin. */
break; break;
case 947: /* stuminlb */ case 948: /* stuminlb */
case 894: /* lduminlb */ case 895: /* lduminlb */
value = 894; /* --> lduminlb. */ value = 895; /* --> lduminlb. */
break; break;
case 948: /* stuminlh */ case 949: /* stuminlh */
case 897: /* lduminlh */ case 898: /* lduminlh */
value = 897; /* --> lduminlh. */ value = 898; /* --> lduminlh. */
break; break;
case 949: /* stuminl */ case 950: /* stuminl */
case 900: /* lduminl */ case 901: /* lduminl */
value = 900; /* --> lduminl. */ value = 901; /* --> lduminl. */
break; break;
case 951: /* mov */ case 952: /* mov */
case 950: /* movn */ case 951: /* movn */
value = 950; /* --> movn. */ value = 951; /* --> movn. */
break; break;
case 953: /* mov */ case 954: /* mov */
case 952: /* movz */ case 953: /* movz */
value = 952; /* --> movz. */ value = 953; /* --> movz. */
break; break;
case 964: /* sevl */ case 965: /* sevl */
case 963: /* sev */ case 964: /* sev */
case 962: /* wfi */ case 963: /* wfi */
case 961: /* wfe */ case 962: /* wfe */
case 960: /* yield */ case 961: /* yield */
case 959: /* nop */ case 960: /* nop */
case 958: /* hint */ case 959: /* hint */
value = 958; /* --> hint. */ value = 959; /* --> hint. */
break; break;
case 973: /* tlbi */ case 974: /* tlbi */
case 972: /* ic */ case 973: /* ic */
case 971: /* dc */ case 972: /* dc */
case 970: /* at */ case 971: /* at */
case 969: /* sys */ case 970: /* sys */
value = 969; /* --> sys. */ value = 970; /* --> sys. */
break; break;
default: return NULL; default: return NULL;
} }

34
opcodes/aarch64-asm.c
View File

@@ -1038,6 +1038,37 @@ convert_bfi_to_bfm (aarch64_inst *inst)
} }
} }
/* The instruction written:
BFC <Xd>, #<lsb>, #<width>
is equivalent to:
BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
static void
convert_bfc_to_bfm (aarch64_inst *inst)
{
int64_t lsb, width;
/* Insert XZR. */
copy_operand_info (inst, 3, 2);
copy_operand_info (inst, 2, 1);
copy_operand_info (inst, 2, 0);
inst->operands[1].reg.regno = 0x1f;
/* Convert the immedate operand. */
lsb = inst->operands[2].imm.value;
width = inst->operands[3].imm.value;
if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
{
inst->operands[2].imm.value = (32 - lsb) & 0x1f;
inst->operands[3].imm.value = width - 1;
}
else
{
inst->operands[2].imm.value = (64 - lsb) & 0x3f;
inst->operands[3].imm.value = width - 1;
}
}
/* The instruction written: /* The instruction written:
LSL <Xd>, <Xn>, #<shift> LSL <Xd>, <Xn>, #<shift>
is equivalent to: is equivalent to:
@@ -1171,6 +1202,9 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
case OP_UBFIZ: case OP_UBFIZ:
convert_bfi_to_bfm (inst); convert_bfi_to_bfm (inst);
break; break;
case OP_BFC:
convert_bfc_to_bfm (inst);
break;
case OP_MOV_V: case OP_MOV_V:
convert_mov_to_orr (inst); convert_mov_to_orr (inst);
break; break;

1097
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

41
opcodes/aarch64-dis.c
View File

@@ -1600,6 +1600,45 @@ convert_bfm_to_bfi (aarch64_inst *inst)
return 0; return 0;
} }
/* The instruction written:
BFC <Xd>, #<lsb>, #<width>
is equivalent to:
BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
static int
convert_bfm_to_bfc (aarch64_inst *inst)
{
int64_t immr, imms, val;
/* Should have been assured by the base opcode value. */
assert (inst->operands[1].reg.regno == 0x1f);
immr = inst->operands[2].imm.value;
imms = inst->operands[3].imm.value;
val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
if (imms < immr)
{
/* Drop XZR from the second operand. */
copy_operand_info (inst, 1, 2);
copy_operand_info (inst, 2, 3);
inst->operands[3].type = AARCH64_OPND_NIL;
/* Recalculate the immediates. */
inst->operands[1].imm.value = (val - immr) & (val - 1);
inst->operands[2].imm.value = imms + 1;
/* The two opcodes have different qualifiers for the operands; reset to
help the checking. */
reset_operand_qualifier (inst, 1);
reset_operand_qualifier (inst, 2);
reset_operand_qualifier (inst, 3);
return 1;
}
return 0;
}
/* The instruction written: /* The instruction written:
LSL <Xd>, <Xn>, #<shift> LSL <Xd>, <Xn>, #<shift>
is equivalent to: is equivalent to:
@@ -1759,6 +1798,8 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
case OP_BFI: case OP_BFI:
case OP_UBFIZ: case OP_UBFIZ:
return convert_bfm_to_bfi (inst); return convert_bfm_to_bfi (inst);
case OP_BFC:
return convert_bfm_to_bfc (inst);
case OP_MOV_V: case OP_MOV_V:
return convert_orr_to_mov (inst); return convert_orr_to_mov (inst);
case OP_MOV_IMM_WIDE: case OP_MOV_IMM_WIDE:

55
opcodes/aarch64-opc-2.c
View File

@@ -121,69 +121,70 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] = static const unsigned op_enum_table [] =
{ {
0, 0,
668,
669, 669,
670, 670,
673, 671,
674, 674,
675, 675,
676, 676,
677, 677,
671,
672,
678, 678,
672,
673,
679, 679,
701, 680,
702, 702,
703, 703,
706, 704,
707, 707,
708, 708,
709, 709,
710, 710,
704,
705,
711, 711,
705,
706,
712, 712,
755, 713,
756, 756,
757, 757,
758, 758,
759,
12, 12,
518,
519, 519,
950, 520,
952,
954,
762,
953,
951, 951,
953,
955,
763,
954,
952,
261, 261,
507, 507,
518,
517, 517,
516, 761,
760, 514,
513, 511,
510,
503, 503,
502, 502,
509, 509,
512, 510,
514, 513,
515, 515,
770, 516,
534, 771,
537,
540,
535, 535,
538, 538,
634, 541,
536,
539,
635,
162, 162,
163, 163,
164, 164,
165, 165,
426, 426,
603, 604,
318, 318,
320, 320,
340, 340,

2
opcodes/aarch64-opc.c
View File

@@ -1659,7 +1659,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break; break;
case AARCH64_OPND_WIDTH: case AARCH64_OPND_WIDTH:
assert (idx == 3 && opnds[idx-1].type == AARCH64_OPND_IMM assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
&& opnds[0].type == AARCH64_OPND_Rd); && opnds[0].type == AARCH64_OPND_Rd);
size = get_upper_bound (qualifier); size = get_upper_bound (qualifier);
if (opnd->imm.value + opnds[idx-1].imm.value > size) if (opnd->imm.value + opnds[idx-1].imm.value > size)

12
opcodes/aarch64-tbl.h
View File

@@ -236,6 +236,13 @@
QLF4(X,X,imm_0_63,imm_0_63), \ QLF4(X,X,imm_0_63,imm_0_63), \
} }
/* e.g. BFC <Wd>, #<immr>, #<imms>. */
#define QL_BF1 \
{ \
QLF3 (W, imm_0_31, imm_1_32), \
QLF3 (X, imm_0_63, imm_1_64), \
}
/* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
#define QL_BF2 \ #define QL_BF2 \
{ \ { \
@@ -1226,6 +1233,8 @@ static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
static const aarch64_feature_set aarch64_feature_rdma = static const aarch64_feature_set aarch64_feature_rdma =
AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
#define CORE &aarch64_feature_v8 #define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp #define FP &aarch64_feature_fp
@@ -1235,6 +1244,7 @@ static const aarch64_feature_set aarch64_feature_rdma =
#define LSE &aarch64_feature_lse #define LSE &aarch64_feature_lse
#define LOR &aarch64_feature_lor #define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma #define RDMA &aarch64_feature_rdma
#define ARMV8_2 &aarch64_feature_v8_2
struct aarch64_opcode aarch64_opcode_table[] = struct aarch64_opcode aarch64_opcode_table[] =
{ {
@@ -1777,6 +1787,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV}, {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
{"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
{"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2,
OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV},
{"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
{"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},