[sim] Run spellcheck.sh in sim (part 1)

Run gdb/contrib/spellcheck.sh on directory sim.

Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...

Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.

Tested by rebuilding on x86_64-linux.

Approved-By: Tom Tromey <tom@tromey.com>

sim/mips/acinclude.m4

@@ -224,7 +224,7 @@ __EOF__
   for fc in ${sim_mips_multi_configs}; do
 
     dnl Split up the entry.  ${c} contains the first three elements.
-    dnl Note: outer sqaure brackets are m4 quotes.
+    dnl Note: outer square brackets are m4 quotes.
     c=`echo ${fc} | sed ['s/:[^:]*$//']`
     bfdmachs=`echo ${fc} | sed 's/.*://'`
     name=`echo ${c} | sed 's/:.*//'`

sim/mips/interp.c

@@ -2579,7 +2579,7 @@ mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
     }
   else if (exception != 0 && mips_cpu->exc_suspended == 0)
     {
-      sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+      sim_io_eprintf(sd, "Warning, ignoring spontaneous exception signal (%d)\n", exception);
     }
   mips_cpu->exc_suspended = 0;
 }

sim/mips/m16.igen

@@ -1049,7 +1049,7 @@
 {
   if (STATE & simDELAYSLOT)
     {
-      return DSPC; /* return saved address of preceeding jmp */
+      return DSPC; /* return saved address of preceding jmp */
     }
   else
     {

sim/mips/mips.igen

@@ -305,9 +305,9 @@
 // suggest they don't.
 //
 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
-// these restrictions, while others, like the VR5500, don't.  To accomodate
+// these restrictions, while others, like the VR5500, don't.  To accommodate
 // such differences, the MIPS IV and MIPS V version of these helper functions
-// use auxillary routines to determine whether the restriction applies.
+// use auxiliary routines to determine whether the restriction applies.
 
 // check_mf_cycles:
 //
@@ -474,7 +474,7 @@
 *micromips32:
 *micromips64:
 {
-  /* FIXME: could record the fact that a stall occured if we want */
+  /* FIXME: could record the fact that a stall occurred if we want */
   int64_t time = sim_events_time (SD);
   hi->op.timestamp = time;
   lo->op.timestamp = time;

sim/mips/sim-main.h

@@ -109,7 +109,7 @@ typedef enum {
 
 /* For some MIPS targets, the HI/LO registers have certain timing
    restrictions in that, for instance, a read of a HI register must be
-   separated by at least three instructions from a preceeding read.
+   separated by at least three instructions from a preceding read.
 
    The struct below is used to record the last access by each of A MT,
    MF or other OP instruction to a HI/LO register.  See mips.igen for
@@ -282,7 +282,7 @@ struct mips_sim_cpu {
 #define simPCOC1         (1 << 18) /* COC[1] from previous */
 #define simDELAYSLOT     (1 << 24) /* 1 = delay slot entry exists */
 #define simSKIPNEXT      (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simSIGINT        (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
+#define simSIGINT        (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occurred */
 #define simJALDELAYSLOT  (1 << 29) /* 1 = in jal delay slot */
 #define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */