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RISC-V: Add support for XCValu extension in CV32E40P

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Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
	* testsuite/gas/riscv/cv-alu-insns.d: New test.
	* testsuite/gas/riscv/cv-alu-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble xcb operand.
	* riscv-opc.c: Defined the MASK and added XCValu instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCValu.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for XCValu.
	(enum riscv_insn_class): Added the XCValu instruction class.
This commit is contained in:
Mary Bennett
2023-10-02 03:02:06 +01:00
committed by Nelson Chu
parent ccb388ca39
commit d1bd9787f9
36 changed files with 787 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
include/opcode/riscv-opc.h
View File

@@ -2357,6 +2357,73 @@
#define MASK_CV_MACURN 0xc000707f
#define MATCH_CV_MACHHURN 0xc000705b
#define MASK_CV_MACHHURN 0xc000707f
/* Vendor-specific (CORE-V) Xcvalu instructions. */
#define MATCH_CV_ABS 0x5000302b
#define MASK_CV_ABS 0xfff0707f
#define MATCH_CV_SLE 0x5200302b
#define MASK_CV_SLE 0xfe00707f
#define MATCH_CV_SLET 0x5200302b
#define MASK_CV_SLET 0xfe00707f
#define MATCH_CV_SLEU 0x5400302b
#define MASK_CV_SLEU 0xfe00707f
#define MATCH_CV_SLETU 0x5400302b
#define MASK_CV_SLETU 0xfe00707f
#define MATCH_CV_MIN 0x5600302b
#define MASK_CV_MIN 0xfe00707f
#define MATCH_CV_MINU 0x5800302b
#define MASK_CV_MINU 0xfe00707f
#define MATCH_CV_MAX 0x5a00302b
#define MASK_CV_MAX 0xfe00707f
#define MATCH_CV_MAXU 0x5c00302b
#define MASK_CV_MAXU 0xfe00707f
#define MATCH_CV_EXTHS 0x6000302b
#define MASK_CV_EXTHS 0xfff0707f
#define MATCH_CV_EXTHZ 0x6200302b
#define MASK_CV_EXTHZ 0xfff0707f
#define MATCH_CV_EXTBS 0x6400302b
#define MASK_CV_EXTBS 0xfff0707f
#define MATCH_CV_EXTBZ 0x6600302b
#define MASK_CV_EXTBZ 0xfff0707f
#define MATCH_CV_CLIP 0x7000302b
#define MASK_CV_CLIP 0xfe00707f
#define MATCH_CV_CLIPU 0x7200302b
#define MASK_CV_CLIPU 0xfe00707f
#define MATCH_CV_CLIPR 0x7400302b
#define MASK_CV_CLIPR 0xfe00707f
#define MATCH_CV_CLIPUR 0x7600302b
#define MASK_CV_CLIPUR 0xfe00707f
#define MATCH_CV_ADDNR 0x8000302b
#define MASK_CV_ADDNR 0xfe00707f
#define MATCH_CV_ADDUNR 0x8200302b
#define MASK_CV_ADDUNR 0xfe00707f
#define MATCH_CV_ADDRNR 0x8400302b
#define MASK_CV_ADDRNR 0xfe00707f
#define MATCH_CV_ADDURNR 0x8600302b
#define MASK_CV_ADDURNR 0xfe00707f
#define MATCH_CV_SUBNR 0x8800302b
#define MASK_CV_SUBNR 0xfe00707f
#define MATCH_CV_SUBUNR 0x8a00302b
#define MASK_CV_SUBUNR 0xfe00707f
#define MATCH_CV_SUBRNR 0x8c00302b
#define MASK_CV_SUBRNR 0xfe00707f
#define MATCH_CV_SUBURNR 0x8e00302b
#define MASK_CV_SUBURNR 0xfe00707f
#define MATCH_CV_ADDN 0x205b
#define MASK_CV_ADDN 0xc000707f
#define MATCH_CV_ADDUN 0x4000205b
#define MASK_CV_ADDUN 0xc000707f
#define MATCH_CV_ADDRN 0x8000205b
#define MASK_CV_ADDRN 0xc000707f
#define MATCH_CV_ADDURN 0xc000205b
#define MASK_CV_ADDURN 0xc000707f
#define MATCH_CV_SUBN 0x305b
#define MASK_CV_SUBN 0xc000707f
#define MATCH_CV_SUBUN 0x4000305b
#define MASK_CV_SUBUN 0xc000707f
#define MATCH_CV_SUBRN 0x8000305b
#define MASK_CV_SUBRN 0xc000707f
#define MATCH_CV_SUBURN 0xc000305b
#define MASK_CV_SUBURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f

5
include/opcode/riscv.h
View File

@@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
/* Vendor-specific (CORE-V) extract macros. */
#define EXTRACT_CV_IS2_UIMM5(x) \
(RV_X(x, 20, 5))
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
@@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
/* Vendor-specific (CORE-V) encode macros. */
#define ENCODE_CV_IS2_UIMM5(x) \
(RV_X(x, 0, 5) << 20)
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
@@ -450,6 +454,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
INSN_CLASS_XCVALU,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,