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Fix decoding of ARM VFP instructions

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-Wduplicated-cond pointed out that arm_record_vfp_data_proc_insn
checks "opc1 == 0x0b" twice.  I filed this a while ago as
PR tdep/20362.

Based on the ARM instruction manual at
https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf, I think the
instruction decoding in this function has two bugs.

First, opc1 is computed as:

  opc1 = bits (arm_insn_r->arm_insn, 20, 23);
[...]
  opc1 = opc1 & 0x04;

This means that tests like:

  else if (opc1 == 0x01)

can never be true.

In the ARM manual, "opc1" corresponds to these bits:

    name   bit
    r      20
    q      21
    D      22
    p      23

... where the D bit is not used for VFP instruction decoding.

So, I believe this code should use ~0x04 instead.

Second, VDIV is recognized by the bits "pqrs" being equal to "1000".
This tranlates to opc1 == 0x08 -- not 0x0b.  Note that pqrs==1001 is
an undefined encoding, which is probably why opc2 is not checked here;
this code doesn't seem to really deal with undefined encodings in
general, so I've left that as is.

I don't have an ARM machine or any reasonable way to test this.

ChangeLog
2018-05-07  Tom Tromey  <tom@tromey.com>

	PR tdep/20362:
	* arm-tdep.c (arm_record_vfp_data_proc_insn): Properly mask off D
	bit.  Use correct value for VDIV.
This commit is contained in:
Tom Tromey
2018-04-21 11:51:34 -06:00
parent 2ceb7719f7
commit ce887586b4
2 changed files with 9 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gdb/ChangeLog
View File

@@ -1,3 +1,9 @@
2018-05-07 Tom Tromey <tom@tromey.com>
PR tdep/20362:
* arm-tdep.c (arm_record_vfp_data_proc_insn): Properly mask off D
bit. Use correct value for VDIV.
2018-05-04 Tom Tromey <tom@tromey.com> 2018-05-04 Tom Tromey <tom@tromey.com>
* configure: Rebuild. * configure: Rebuild.

5
gdb/arm-tdep.c
View File

@@ -11421,7 +11421,8 @@ arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
opc3 = bits (arm_insn_r->arm_insn, 6, 7); opc3 = bits (arm_insn_r->arm_insn, 6, 7);
dp_op_sz = bit (arm_insn_r->arm_insn, 8); dp_op_sz = bit (arm_insn_r->arm_insn, 8);
bit_d = bit (arm_insn_r->arm_insn, 22); bit_d = bit (arm_insn_r->arm_insn, 22);
opc1 = opc1 & 0x04; /* Mask off the "D" bit. */
opc1 = opc1 & ~0x04;
/* Handle VMLA, VMLS. */ /* Handle VMLA, VMLS. */
if (opc1 == 0x00) if (opc1 == 0x00)
@@ -11486,7 +11487,7 @@ arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
} }
} }
/* Handle VDIV. */ /* Handle VDIV. */
else if (opc1 == 0x0b) else if (opc1 == 0x08)
{ {
if (dp_op_sz) if (dp_op_sz)
curr_insn_type = INSN_T1; curr_insn_type = INSN_T1;