forked from Imagelibrary/binutils-gdb
aarch64: Add the SME2 saturating conversion instructions
There are two instruction formats here: - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers.
This commit is contained in:
Richard Sandiford
3
gas/testsuite/gas/aarch64/sme2-25-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-25-invalid.d
Normal file
@@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-25-invalid.s
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#error_output: sme2-25-invalid.l
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48
gas/testsuite/gas/aarch64/sme2-25-invalid.l
Normal file
48
gas/testsuite/gas/aarch64/sme2-25-invalid.l
Normal file
@@ -0,0 +1,48 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvt 0,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvt z0\.h,0'
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z1\.d}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z1\.d}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s}
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `sqcvt z0\.h,{z0\.s,z8\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z31\.s,z0\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z1\.s-z4\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z2\.s-z5\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z3\.s-z6\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z1\.d}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z2\.d}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.d-z4\.d}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z2\.d-z5\.d}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z3\.d-z6\.d}'
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28
gas/testsuite/gas/aarch64/sme2-25-invalid.s
Normal file
28
gas/testsuite/gas/aarch64/sme2-25-invalid.s
Normal file
@@ -0,0 +1,28 @@
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sqcvt 0, { z0.s - z1.s }
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sqcvt z0.h, 0
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sqcvt z0.s, { z0.s - z1.s }
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sqcvt z0.b, { z0.d - z1.d }
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sqcvt z0.s, { z0.d - z1.d }
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sqcvt z0.s, { z0.s - z3.s }
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sqcvt z0.b, { z0.d - z3.d }
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sqcvt z0.s, { z0.d - z3.d }
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sqcvt z0.h, { z0.s - z2.s }
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sqcvt z0.h, { z0.s - z3.s }
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sqcvt z0.h, { z0.s, z8.s }
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sqcvt z0.h, { z1.s - z2.s }
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sqcvt z0.h, { z31.s, z0.s }
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sqcvt z0.b, { z0.s - z1.s }
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sqcvt z0.b, { z0.s - z2.s }
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sqcvt z0.b, { z1.s - z4.s }
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sqcvt z0.b, { z2.s - z5.s }
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sqcvt z0.b, { z3.s - z6.s }
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sqcvt z0.h, { z0.d - z1.d }
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sqcvt z0.h, { z0.d - z2.d }
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sqcvt z0.h, { z1.d - z4.d }
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sqcvt z0.h, { z2.d - z5.d }
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sqcvt z0.h, { z3.d - z6.d }
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3
gas/testsuite/gas/aarch64/sme2-25-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-25-noarch.d
Normal file
@@ -0,0 +1,3 @@
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#as: -march=armv8-a+sme
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#source: sme2-25.s
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#error_output: sme2-25-noarch.l
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37
gas/testsuite/gas/aarch64/sme2-25-noarch.l
Normal file
37
gas/testsuite/gas/aarch64/sme2-25-noarch.l
Normal file
@@ -0,0 +1,37 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z30\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z19\.h,{z14\.s-z15\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z28\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z11\.b,{z20\.s-z23\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z28\.d-z31\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z22\.h,{z4\.d-z7\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z30\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z19\.h,{z14\.s-z15\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z28\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z11\.b,{z20\.s-z23\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z28\.d-z31\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z22\.h,{z4\.d-z7\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z30\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z19\.h,{z14\.s-z15\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.b,{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z28\.s-z31\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z11\.b,{z20\.s-z23\.s}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.d-z3\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z28\.d-z31\.d}'
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[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z22\.h,{z4\.d-z7\.d}'
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45
gas/testsuite/gas/aarch64/sme2-25.d
Normal file
45
gas/testsuite/gas/aarch64/sme2-25.d
Normal file
@@ -0,0 +1,45 @@
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#as: -march=armv8-a+sme2
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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[^:]+: c123e000 sqcvt z0\.h, {z0\.s-z1\.s}
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[^:]+: c123e01f sqcvt z31\.h, {z0\.s-z1\.s}
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[^:]+: c123e3c0 sqcvt z0\.h, {z30\.s-z31\.s}
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[^:]+: c123e1d3 sqcvt z19\.h, {z14\.s-z15\.s}
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[^:]+: c133e000 sqcvt z0\.b, {z0\.s-z3\.s}
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[^:]+: c133e01f sqcvt z31\.b, {z0\.s-z3\.s}
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[^:]+: c133e380 sqcvt z0\.b, {z28\.s-z31\.s}
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[^:]+: c133e28b sqcvt z11\.b, {z20\.s-z23\.s}
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[^:]+: c1b3e000 sqcvt z0\.h, {z0\.d-z3\.d}
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[^:]+: c1b3e01f sqcvt z31\.h, {z0\.d-z3\.d}
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[^:]+: c1b3e380 sqcvt z0\.h, {z28\.d-z31\.d}
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[^:]+: c1b3e096 sqcvt z22\.h, {z4\.d-z7\.d}
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[^:]+: c163e000 sqcvtu z0\.h, {z0\.s-z1\.s}
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[^:]+: c163e01f sqcvtu z31\.h, {z0\.s-z1\.s}
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[^:]+: c163e3c0 sqcvtu z0\.h, {z30\.s-z31\.s}
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[^:]+: c163e1d3 sqcvtu z19\.h, {z14\.s-z15\.s}
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[^:]+: c173e000 sqcvtu z0\.b, {z0\.s-z3\.s}
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[^:]+: c173e01f sqcvtu z31\.b, {z0\.s-z3\.s}
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[^:]+: c173e380 sqcvtu z0\.b, {z28\.s-z31\.s}
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[^:]+: c173e28b sqcvtu z11\.b, {z20\.s-z23\.s}
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[^:]+: c1f3e000 sqcvtu z0\.h, {z0\.d-z3\.d}
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[^:]+: c1f3e01f sqcvtu z31\.h, {z0\.d-z3\.d}
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[^:]+: c1f3e380 sqcvtu z0\.h, {z28\.d-z31\.d}
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[^:]+: c1f3e096 sqcvtu z22\.h, {z4\.d-z7\.d}
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[^:]+: c123e020 uqcvt z0\.h, {z0\.s-z1\.s}
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[^:]+: c123e03f uqcvt z31\.h, {z0\.s-z1\.s}
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[^:]+: c123e3e0 uqcvt z0\.h, {z30\.s-z31\.s}
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[^:]+: c123e1f3 uqcvt z19\.h, {z14\.s-z15\.s}
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[^:]+: c133e020 uqcvt z0\.b, {z0\.s-z3\.s}
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[^:]+: c133e03f uqcvt z31\.b, {z0\.s-z3\.s}
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[^:]+: c133e3a0 uqcvt z0\.b, {z28\.s-z31\.s}
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[^:]+: c133e2ab uqcvt z11\.b, {z20\.s-z23\.s}
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[^:]+: c1b3e020 uqcvt z0\.h, {z0\.d-z3\.d}
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[^:]+: c1b3e03f uqcvt z31\.h, {z0\.d-z3\.d}
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[^:]+: c1b3e3a0 uqcvt z0\.h, {z28\.d-z31\.d}
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[^:]+: c1b3e0b6 uqcvt z22\.h, {z4\.d-z7\.d}
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44
gas/testsuite/gas/aarch64/sme2-25.s
Normal file
44
gas/testsuite/gas/aarch64/sme2-25.s
Normal file
@@ -0,0 +1,44 @@
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sqcvt z0.h, { z0.s - z1.s }
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sqcvt z31.h, { z0.s - z1.s }
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sqcvt z0.h, { z30.s - z31.s }
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sqcvt z19.h, { z14.s - z15.s }
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sqcvt z0.b, { z0.s - z3.s }
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sqcvt z31.b, { z0.s - z3.s }
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sqcvt z0.b, { z28.s - z31.s }
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sqcvt z11.b, { z20.s - z23.s }
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sqcvt z0.h, { z0.d - z3.d }
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sqcvt z31.h, { z0.d - z3.d }
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sqcvt z0.h, { z28.d - z31.d }
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sqcvt z22.h, { z4.d - z7.d }
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sqcvtu z0.h, { z0.s - z1.s }
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sqcvtu z31.h, { z0.s - z1.s }
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sqcvtu z0.h, { z30.s - z31.s }
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sqcvtu z19.h, { z14.s - z15.s }
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sqcvtu z0.b, { z0.s - z3.s }
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sqcvtu z31.b, { z0.s - z3.s }
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sqcvtu z0.b, { z28.s - z31.s }
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sqcvtu z11.b, { z20.s - z23.s }
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sqcvtu z0.h, { z0.d - z3.d }
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sqcvtu z31.h, { z0.d - z3.d }
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sqcvtu z0.h, { z28.d - z31.d }
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sqcvtu z22.h, { z4.d - z7.d }
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uqcvt z0.h, { z0.s - z1.s }
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uqcvt z31.h, { z0.s - z1.s }
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uqcvt z0.h, { z30.s - z31.s }
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uqcvt z19.h, { z14.s - z15.s }
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uqcvt z0.b, { z0.s - z3.s }
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uqcvt z31.b, { z0.s - z3.s }
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uqcvt z0.b, { z28.s - z31.s }
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uqcvt z11.b, { z20.s - z23.s }
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uqcvt z0.h, { z0.d - z3.d }
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uqcvt z31.h, { z0.d - z3.d }
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uqcvt z0.h, { z28.d - z31.d }
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uqcvt z22.h, { z4.d - z7.d }
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3
gas/testsuite/gas/aarch64/sme2-26-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-26-invalid.d
Normal file
@@ -0,0 +1,3 @@
|
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#as: -march=armv8-a
|
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#source: sme2-26-invalid.s
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#error_output: sme2-26-invalid.l
|
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13
gas/testsuite/gas/aarch64/sme2-26-invalid.l
Normal file
13
gas/testsuite/gas/aarch64/sme2-26-invalid.l
Normal file
@@ -0,0 +1,13 @@
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[^ :]+: Assembler messages:
|
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvtn 0,{z0\.s-z3\.s}'
|
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[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvtn z0\.b,0'
|
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z1\.s}'
|
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z2\.s}'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z1\.s-z4\.s}'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z2\.s-z5\.s}'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z3\.s-z6\.s}'
|
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z1\.d-z4\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z2\.d-z5\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z3\.d-z6\.d}'
|
||||
14
gas/testsuite/gas/aarch64/sme2-26-invalid.s
Normal file
14
gas/testsuite/gas/aarch64/sme2-26-invalid.s
Normal file
@@ -0,0 +1,14 @@
|
||||
sqcvtn 0, { z0.s - z3.s }
|
||||
sqcvtn z0.b, 0
|
||||
|
||||
sqcvtn z0.b, { z0.s - z1.s }
|
||||
sqcvtn z0.b, { z0.s - z2.s }
|
||||
sqcvtn z0.b, { z1.s - z4.s }
|
||||
sqcvtn z0.b, { z2.s - z5.s }
|
||||
sqcvtn z0.b, { z3.s - z6.s }
|
||||
|
||||
sqcvtn z0.h, { z0.d - z1.d }
|
||||
sqcvtn z0.h, { z0.d - z2.d }
|
||||
sqcvtn z0.h, { z1.d - z4.d }
|
||||
sqcvtn z0.h, { z2.d - z5.d }
|
||||
sqcvtn z0.h, { z3.d - z6.d }
|
||||
3
gas/testsuite/gas/aarch64/sme2-26-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-26-noarch.d
Normal file
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-26.s
|
||||
#error_output: sme2-26-noarch.l
|
||||
25
gas/testsuite/gas/aarch64/sme2-26-noarch.l
Normal file
25
gas/testsuite/gas/aarch64/sme2-26-noarch.l
Normal file
@@ -0,0 +1,25 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z11\.b,{z20\.s-z23\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z22\.h,{z4\.d-z7\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z11\.b,{z20\.s-z23\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z22\.h,{z4\.d-z7\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.b,{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z11\.b,{z20\.s-z23\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.h,{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z22\.h,{z4\.d-z7\.d}'
|
||||
33
gas/testsuite/gas/aarch64/sme2-26.d
Normal file
33
gas/testsuite/gas/aarch64/sme2-26.d
Normal file
@@ -0,0 +1,33 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c133e040 sqcvtn z0\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c133e05f sqcvtn z31\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c133e3c0 sqcvtn z0\.b, {z28\.s-z31\.s}
|
||||
[^:]+: c133e2cb sqcvtn z11\.b, {z20\.s-z23\.s}
|
||||
[^:]+: c1b3e040 sqcvtn z0\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1b3e05f sqcvtn z31\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1b3e3c0 sqcvtn z0\.h, {z28\.d-z31\.d}
|
||||
[^:]+: c1b3e0d6 sqcvtn z22\.h, {z4\.d-z7\.d}
|
||||
[^:]+: c173e040 sqcvtun z0\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c173e05f sqcvtun z31\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c173e3c0 sqcvtun z0\.b, {z28\.s-z31\.s}
|
||||
[^:]+: c173e2cb sqcvtun z11\.b, {z20\.s-z23\.s}
|
||||
[^:]+: c1f3e040 sqcvtun z0\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1f3e05f sqcvtun z31\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1f3e3c0 sqcvtun z0\.h, {z28\.d-z31\.d}
|
||||
[^:]+: c1f3e0d6 sqcvtun z22\.h, {z4\.d-z7\.d}
|
||||
[^:]+: c133e060 uqcvtn z0\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c133e07f uqcvtn z31\.b, {z0\.s-z3\.s}
|
||||
[^:]+: c133e3e0 uqcvtn z0\.b, {z28\.s-z31\.s}
|
||||
[^:]+: c133e2eb uqcvtn z11\.b, {z20\.s-z23\.s}
|
||||
[^:]+: c1b3e060 uqcvtn z0\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1b3e07f uqcvtn z31\.h, {z0\.d-z3\.d}
|
||||
[^:]+: c1b3e3e0 uqcvtn z0\.h, {z28\.d-z31\.d}
|
||||
[^:]+: c1b3e0f6 uqcvtn z22\.h, {z4\.d-z7\.d}
|
||||
29
gas/testsuite/gas/aarch64/sme2-26.s
Normal file
29
gas/testsuite/gas/aarch64/sme2-26.s
Normal file
@@ -0,0 +1,29 @@
|
||||
sqcvtn z0.b, { z0.s - z3.s }
|
||||
sqcvtn z31.b, { z0.s - z3.s }
|
||||
sqcvtn z0.b, { z28.s - z31.s }
|
||||
sqcvtn z11.b, { z20.s - z23.s }
|
||||
|
||||
sqcvtn z0.h, { z0.d - z3.d }
|
||||
sqcvtn z31.h, { z0.d - z3.d }
|
||||
sqcvtn z0.h, { z28.d - z31.d }
|
||||
sqcvtn z22.h, { z4.d - z7.d }
|
||||
|
||||
sqcvtun z0.b, { z0.s - z3.s }
|
||||
sqcvtun z31.b, { z0.s - z3.s }
|
||||
sqcvtun z0.b, { z28.s - z31.s }
|
||||
sqcvtun z11.b, { z20.s - z23.s }
|
||||
|
||||
sqcvtun z0.h, { z0.d - z3.d }
|
||||
sqcvtun z31.h, { z0.d - z3.d }
|
||||
sqcvtun z0.h, { z28.d - z31.d }
|
||||
sqcvtun z22.h, { z4.d - z7.d }
|
||||
|
||||
uqcvtn z0.b, { z0.s - z3.s }
|
||||
uqcvtn z31.b, { z0.s - z3.s }
|
||||
uqcvtn z0.b, { z28.s - z31.s }
|
||||
uqcvtn z11.b, { z20.s - z23.s }
|
||||
|
||||
uqcvtn z0.h, { z0.d - z3.d }
|
||||
uqcvtn z31.h, { z0.d - z3.d }
|
||||
uqcvtn z0.h, { z28.d - z31.d }
|
||||
uqcvtn z22.h, { z4.d - z7.d }
|
||||
@@ -717,6 +717,7 @@ enum aarch64_insn_class
|
||||
sme_size_12_hs,
|
||||
sme_size_22,
|
||||
sme_size_22_hsd,
|
||||
sme_sz_23,
|
||||
sme_str,
|
||||
sme_start,
|
||||
sme_stop,
|
||||
|
||||
@@ -1970,6 +1970,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
|
||||
aarch64_get_variant (inst) + 1, 0);
|
||||
break;
|
||||
|
||||
case sme_sz_23:
|
||||
insert_field (FLD_SME_sz_23, &inst->value,
|
||||
aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
case sve_cpy:
|
||||
insert_fields (&inst->value, aarch64_get_variant (inst),
|
||||
0, 2, FLD_SVE_M_14, FLD_size);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -3102,6 +3102,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
|
||||
variant -= 1;
|
||||
break;
|
||||
|
||||
case sme_sz_23:
|
||||
variant = extract_field (FLD_SME_sz_23, inst->value, 0);
|
||||
break;
|
||||
|
||||
case sve_cpy:
|
||||
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
|
||||
break;
|
||||
|
||||
@@ -252,6 +252,7 @@ const aarch64_field fields[] =
|
||||
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
|
||||
{ 12, 2 }, /* SME_size_12: bits [13:12]. */
|
||||
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
|
||||
{ 23, 1 }, /* SME_sz_23: bit [23]. */
|
||||
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
|
||||
{ 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
|
||||
{ 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
|
||||
|
||||
@@ -73,6 +73,7 @@ enum aarch64_field_kind
|
||||
FLD_SME_i1,
|
||||
FLD_SME_size_12,
|
||||
FLD_SME_size_22,
|
||||
FLD_SME_sz_23,
|
||||
FLD_SME_tszh,
|
||||
FLD_SME_tszl,
|
||||
FLD_SME_zero_mask,
|
||||
|
||||
@@ -2128,6 +2128,11 @@
|
||||
QLF2(S_D,S_D), \
|
||||
QLF2(S_Q,S_Q), \
|
||||
}
|
||||
#define OP_SVE_VV_BH_SD \
|
||||
{ \
|
||||
QLF2(S_B,S_S), \
|
||||
QLF2(S_H,S_D), \
|
||||
}
|
||||
#define OP_SVE_VV_HSD \
|
||||
{ \
|
||||
QLF2(S_H,S_H), \
|
||||
@@ -5608,6 +5613,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("smlsll", 0xc1a10008, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("smopa", 0xa0800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
|
||||
SME2_INSN ("smops", 0xa0800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
|
||||
SME2_INSN ("sqcvt", 0xc123e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
|
||||
SME2_INSN ("sqcvt", 0xc133e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("sqcvtn", 0xc133e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("sqcvtu", 0xc163e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
|
||||
SME2_INSN ("sqcvtu", 0xc173e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("sqcvtun", 0xc173e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("sqdmulh", 0xc120a400, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
|
||||
@@ -5757,6 +5768,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("umlsll", 0xc1a10018, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0),
|
||||
SME2_INSN ("umopa", 0xa1800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
|
||||
SME2_INSN ("umops", 0xa1800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0),
|
||||
SME2_INSN ("uqcvt", 0xc123e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),
|
||||
SME2_INSN ("uqcvt", 0xc133e020, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("uqcvtn", 0xc133e060, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0),
|
||||
SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1),
|
||||
|
||||
Reference in New Issue
Block a user