* Makefile.in (sim-options_h): Define.

(sim-{module,options,trace,profile,utils}.o): Clean up dependencies.
	(sim-model.o): Add new rule.
	(cgen-{scache,trace,utils}.o): Add new rules.
	* aclocal.m4 (SIM_AC_OPTION_{SCACHE,DEFAULT_MODEL}): Add.
	* cgen-scache.c (scache_print_profile): Change `sd' arg to `cpu'.
	Indent output by 2 spaces.
	* cgen-scache.h (scache_print_profile): Update.
	* cgen-trace.c (trace_insn_fini): Indent output by 2 spaces.
	Use trace_printf, not fprintf.
	(trace_extract): Use trace_printf, not cgen_trace_printf.
	* genmloop.sh (!FAST case): Increment `insn_count'.
	* sim-base.h (sim_state_base): Only include scache_size if WITH_SCACHE.
	(sim_cpu_base): Rename member `sd' to `state' to be consistent with
	access macro's name.
	* sim-core.c (sim_core_init): Use EXTERN_SIM_CORE to define it.
	Change return type to SIM_RC.
	(sim_core_{install,uninstall}): New functions.
	* sim-core.h (sim_core_{install,uninstall}): Declare.
	(sim_core_init): Use EXTERN_SIM_CORE to define it.
	Change return type to SIM_RC.
	* sim-model.h (models,machs,model_install): Declare.
	* sim-module.c (modules): Add scache_install, model_install.
	(sim_post_argv_init): Set cpu->state backlinks.
	* sim-options.c (standard_options): Delete --simcache-size,--max-insns.
	(standard_option_handler): Likewise.
	* sim-profile.c (PROFILE_{HISTOGRAM,LABEL}_WIDTH): Move to
	sim-profile.h.
	(*): Assume ANSI C.
	(profile_options): Delete --profile-simcache.
	(profile_option_handler): Likewise.
	(profile_print_insn): Change `sd' arg to `cpu'.  Indent output 2
	spaces.
	(profile_print_{memory,model}): Likewise.
	(profile_print_simcache): Delete.
	(profile_print_speed): New function.
	(profile_print): Rewrite.
	* sim-profile.h (PROFILE_scache): Renamed from PROFILE_simcache.
	(WITH_PROFILE_SCACHE_P): Renamed from WITH_PROFILE_SIMCACHE_P.
	(PROFILE_DATA): Delete members simcache_{hits,misses}.
	(PROFILE_COUNT_SIMCACHE_{HIT,MISS}): Delete.
	(PROFILE_{CALLBACK,CPU_CALLBACK}): New types.
	(profile_print): Update prototype.

sim/common/sim-core.h

@@ -0,0 +1,169 @@
+/*  This file is part of the program psim.
+
+    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+ 
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 
+    */
+
+
+#ifndef _SIM_CORE_H_
+#define _SIM_CORE_H_
+
+
+/* basic types */
+
+typedef struct _sim_core_mapping sim_core_mapping;
+struct _sim_core_mapping {
+  /* common */
+  int level;
+  int space;
+  unsigned_word base;
+  unsigned_word bound;
+  unsigned nr_bytes;
+  /* memory map */
+  int free_buffer;
+  void *buffer;
+  /* callback map */
+  device *device;
+  /* growth */
+  sim_core_mapping *next;
+};
+
+typedef struct _sim_core_map sim_core_map;
+struct _sim_core_map {
+  sim_core_mapping *first;
+};
+
+typedef enum {
+  sim_core_read_map,
+  sim_core_write_map,
+  sim_core_execute_map,
+  nr_sim_core_maps,
+} sim_core_maps;
+
+typedef struct _sim_core sim_core;
+struct _sim_core {
+  int trace;
+  sim_core_map map[nr_sim_core_maps];
+};
+
+
+/* Install the "core" module.  */
+
+EXTERN_SIM_CORE\
+(SIM_RC) sim_core_install (SIM_DESC sd);
+
+
+/* Uninstall the "core" subsystem.  */
+
+EXTERN_SIM_CORE\
+(void)
+sim_core_uninstall (SIM_DESC sd);
+
+
+/* initialize */
+
+EXTERN_SIM_CORE\
+(SIM_RC) sim_core_init
+(SIM_DESC sd);
+
+
+/* tracing */
+
+INLINE_SIM_CORE\
+(void) sim_core_set_trace\
+(SIM_DESC sd,
+ int level);
+
+
+
+/* Create a memory space within the core. */
+
+INLINE_SIM_CORE\
+(void) sim_core_attach
+(SIM_DESC sd,
+ attach_type attach,
+ access_type access,
+ int address_space,
+ unsigned_word addr,
+ unsigned nr_bytes, /* host limited */
+ device *client,
+ void *optional_buffer);
+
+
+
+/* Variable sized read/write
+
+   Transfer (zero) a variable size block of data between the host and
+   target (possibly byte swapping it).  Should any problems occure,
+   the number of bytes actually transfered is returned. */
+
+INLINE_SIM_CORE\
+(unsigned) sim_core_read_buffer
+(SIM_DESC sd,
+ sim_core_maps map,
+ void *buffer,
+ unsigned_word addr,
+ unsigned nr_bytes);
+
+INLINE_SIM_CORE\
+(unsigned) sim_core_write_buffer
+(SIM_DESC sd,
+ sim_core_maps map,
+ const void *buffer,
+ unsigned_word addr,
+ unsigned nr_bytes);
+
+
+/* Fixed sized read/write
+
+   Transfer a fixed amout of memory between the host and target.  The
+   memory always being translated and the operation always aborting
+   should a problem occure */
+
+#define DECLARE_SIM_CORE_WRITE_N(N) \
+INLINE_SIM_CORE\
+(void) sim_core_write_##N \
+(SIM_DESC sd, \
+ sim_core_maps map, \
+ unsigned_word addr, \
+ unsigned_##N val);
+
+DECLARE_SIM_CORE_WRITE_N(1)
+DECLARE_SIM_CORE_WRITE_N(2)
+DECLARE_SIM_CORE_WRITE_N(4)
+DECLARE_SIM_CORE_WRITE_N(8)
+DECLARE_SIM_CORE_WRITE_N(word)
+
+#undef DECLARE_SIM_CORE_WRITE_N
+
+
+#define DECLARE_SIM_CORE_READ_N(N) \
+INLINE_SIM_CORE\
+(unsigned_##N) sim_core_read_##N \
+(SIM_DESC sd, \
+ sim_core_maps map, \
+ unsigned_word addr);
+
+DECLARE_SIM_CORE_READ_N(1)
+DECLARE_SIM_CORE_READ_N(2)
+DECLARE_SIM_CORE_READ_N(4)
+DECLARE_SIM_CORE_READ_N(8)
+DECLARE_SIM_CORE_READ_N(word)
+
+#undef DECLARE_SIM_CORE_READ_N
+
+#endif