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[ARM] Add ARMv8.3 VCMLA and VCADD instructions

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Add support for VCMLA and VCADD advanced SIMD complex number instructions.

The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.

In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.

gas/
	* config/tc-arm.c (do_vcmla, do_vcadd): Define.
	(neon_scalar_for_vcmla): Define.
	(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
	(NEON_ENC_TAB): Add DDSI and QQSI variants.
	(insns): Add vcmla and vcadd.
	* testsuite/gas/arm/armv8_3-a-simd.d: New.
	* testsuite/gas/arm/armv8_3-a-simd.s: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
	* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
	(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
This commit is contained in:
Szabolcs Nagy
2016-12-05 14:24:17 +00:00
parent 0691188992
commit c28eeff2ea
9 changed files with 314 additions and 0 deletions
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28
opcodes/arm-dis.c
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@@ -116,6 +116,7 @@ struct opcode16
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>V print as a NEON D or Q register
%<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
@@ -882,6 +883,28 @@ static const struct opcode32 coprocessor_opcodes[] =
0xfc400000, 0xfff00000,
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
/* V5 coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
@@ -3673,10 +3696,15 @@ print_insn_coprocessor (bfd_vma pc,
}
func (stream, "%s", arm_regnames[value]);
break;
case 'V':
if (given & (1 << 6))
goto Q;
/* FALLTHROUGH */
case 'D':
func (stream, "d%ld", value);
break;
case 'Q':
Q:
if (value & 1)
func (stream, "<illegal reg q%ld.5>", value >> 1);
else