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bpf: opcodes, gas: support for signed load V4 instructions

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This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
	instructions.
	(BPF_MODE_SMEM): Define.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
	instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Add signed load instructions.
	* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
	* testsuite/gas/bpf/mem.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Instructions): Document the signed load
	instructions.
This commit is contained in:
Jose E. Marchesi
2023-07-21 19:47:49 +02:00
parent 2f3dbc5fb5
commit c24fd9547f
12 changed files with 78 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
gas/ChangeLog
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@@ -1,3 +1,13 @@
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu.s: Test movs instructions.

20
gas/doc/c-bpf.texi
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@@ -483,6 +483,26 @@ Generic 16-bit load.
Generic 8-bit load. Generic 8-bit load.
@end table @end table
Signed load to register instructions:
@table @code
@item ldxsdw rd, [rs + offset16]
@itemx rd = *(i64 *) (rs + offset16)
Generic 64-bit signed load.
@item ldxsw rd, [rs + offset16]
@itemx rd = *(i32 *) (rs + offset16)
Generic 32-bit signed load.
@item ldxsh rd, [rs + offset16]
@itemx rd = *(i16 *) (rs + offset16)
Generic 16-bit signed load.
@item ldxsb rd, [rs + offset16]
@itemx rd = *(i8 *) (rs + offset16)
Generic 8-bit signed load.
@end table
Store from register instructions: Store from register instructions:
@table @code @table @code

4
gas/testsuite/gas/bpf/mem-be-pseudoc.d
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@@ -28,3 +28,7 @@ Disassembly of section .text:
88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
a0: 81 21 7e ef 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\)
a8: 89 21 7e ef 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\)
b0: 91 21 7e ef 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\)
b8: 99 21 7e ef 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\)

4
gas/testsuite/gas/bpf/mem-be.d
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@@ -28,3 +28,7 @@ Disassembly of section .text:
88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344
90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344
98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344
a0: 81 21 7e ef 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\]
a8: 89 21 7e ef 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\]
b0: 91 21 7e ef 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\]
b8: 99 21 7e ef 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\]

4
gas/testsuite/gas/bpf/mem-pseudoc.d
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@@ -28,3 +28,7 @@ Disassembly of section .text:
88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344
a0: 81 12 ef 7e 00 00 00 00 r2=\*\(i32\*\)\(r1\+0x7eef\)
a8: 89 12 ef 7e 00 00 00 00 r2=\*\(i16\*\)\(r1\+0x7eef\)
b0: 91 12 ef 7e 00 00 00 00 r2=\*\(i8\*\)\(r1\+0x7eef\)
b8: 99 12 ef 7e 00 00 00 00 r2=\*\(i64\*\)\(r1\+0x7eef\)

4
gas/testsuite/gas/bpf/mem-pseudoc.s
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@@ -21,3 +21,7 @@
*(u16 *)(r1 + 0x7eef) = 0x11223344 *(u16 *)(r1 + 0x7eef) = 0x11223344
*(u32 *)(r1 + 0x7eef) = 0x11223344 *(u32 *)(r1 + 0x7eef) = 0x11223344
*(u64 *)(r1 + -2) = 0x11223344 *(u64 *)(r1 + -2) = 0x11223344
r2 = *(i32*)(r1+0x7eef)
r2 = *(i16*)(r1+0x7eef)
r2 = *(i8*)(r1+0x7eef)
r2 = *(i64*)(r1+0x7eef)

4
gas/testsuite/gas/bpf/mem.d
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@@ -28,3 +28,7 @@ Disassembly of section .text:
88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344
a0: 81 12 ef 7e 00 00 00 00 ldxsw %r2,\[%r1\+0x7eef\]
a8: 89 12 ef 7e 00 00 00 00 ldxsh %r2,\[%r1\+0x7eef\]
b0: 91 12 ef 7e 00 00 00 00 ldxsb %r2,\[%r1\+0x7eef\]
b8: 99 12 ef 7e 00 00 00 00 ldxsdw %r2,\[%r1\+0x7eef\]

4
gas/testsuite/gas/bpf/mem.s
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@@ -22,3 +22,7 @@
sth [%r1+0x7eef], 0x11223344 sth [%r1+0x7eef], 0x11223344
stw [%r1+0x7eef], 0x11223344 stw [%r1+0x7eef], 0x11223344
stdw [%r1-2], 0x11223344 stdw [%r1-2], 0x11223344
ldxsw %r2, [%r1+0x7eef]
ldxsh %r2, [%r1+0x7eef]
ldxsb %r2, [%r1+0x7eef]
ldxsdw %r2, [%r1+0x7eef]

6
include/ChangeLog
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@@ -1,3 +1,9 @@
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.

3
include/opcode/bpf.h
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@@ -112,6 +112,7 @@ typedef uint64_t bpf_insn_word;
#define BPF_MODE_IND ((uint64_t)0x40 << 56) #define BPF_MODE_IND ((uint64_t)0x40 << 56)
#define BPF_MODE_MEM ((uint64_t)0x60 << 56) #define BPF_MODE_MEM ((uint64_t)0x60 << 56)
#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56) #define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)
#define BPF_MODE_SMEM ((uint64_t)0x80 << 56)
#define BPF_SIZE_W ((uint64_t)0x00 << 56) #define BPF_SIZE_W ((uint64_t)0x00 << 56)
#define BPF_SIZE_H ((uint64_t)0x08 << 56) #define BPF_SIZE_H ((uint64_t)0x08 << 56)
@@ -186,6 +187,8 @@ enum bpf_insn_id
BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW, BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,
/* Generic load instructions (to register.) */ /* Generic load instructions (to register.) */
BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW, BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
/* Generic signed load instructions. */
BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW,
/* Generic store instructions (from register.) */ /* Generic store instructions (from register.) */
BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR, BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,
BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI, BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,

5
opcodes/ChangeLog
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@@ -1,3 +1,8 @@
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
instructions.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and

10
opcodes/bpf-opc.c
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@@ -217,6 +217,16 @@ const struct bpf_opcode bpf_opcodes[] =
{BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )", {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM}, BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
/* Generic signed load instructions (to register.) */
{BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( i8 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_SMEM},
{BPF_INSN_LDXSH, "ldxsh%W%dr , [ %sr %o16 ]", "%dr = * ( i16 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_SMEM},
{BPF_INSN_LDXSW, "ldxsw%W%dr , [ %sr %o16 ]", "%dr = * ( i32 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_SMEM},
{BPF_INSN_LDXSDW, "ldxsdw%W%dr , [ %sr %o16 ]","%dr = * ( i64 * ) ( %sr %o16 )",
BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_SMEM},
/* Generic store instructions (from register.) */ /* Generic store instructions (from register.) */
{BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr", {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr",
BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM}, BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM},