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aarch64: Add BC instruction

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This patch adds support for the Armv8.8-A BC instruction.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en]

include/
	* opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro.
	(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC.

opcodes/
	* aarch64-tbl.h (aarch64_feature_hbc): New variable.
	(HBC, HBC_INSN): New macros.
	(aarch64_opcode_table): Add BC.C.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document +hbc.
	* config/tc-aarch64.c (aarch64_features): Add "hbc".
	* testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test.
	* testsuite/gas/aarch64/hbc-invalid.s,
	testsuite/gas/aarch64/hbc-invalid.l,
	testsuite/gas/aarch64/hbc-invalid.d: New test.
This commit is contained in:
Richard Sandiford
2021-12-02 15:00:57 +00:00
parent 63eff94751
commit bcca550b3d
10 changed files with 169 additions and 59 deletions
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4
include/opcode/aarch64.h
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@@ -88,6 +88,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
#define AARCH64_FEATURE_MOPS (1ULL << 50) /* Standardization of memory operations. */
#define AARCH64_FEATURE_HBC (1ULL << 51) /* Hinted conditional branches. */
#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
#define AARCH64_FEATURE_F32MM (1ULL << 53)
#define AARCH64_FEATURE_F64MM (1ULL << 54)
@@ -145,7 +146,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_LS64)
#define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \
AARCH64_FEATURE_V8_8 \
| AARCH64_FEATURE_MOPS)
| AARCH64_FEATURE_MOPS \
| AARCH64_FEATURE_HBC)
#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
AARCH64_FEATURE_V8_R) \
& ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))