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For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping

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through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
This commit is contained in:
Andrew Cagney
1997-12-08 03:22:58 +00:00
parent 0a5875fc63
commit bc6df23d14
4 changed files with 172 additions and 87 deletions
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7
sim/testsuite/d10v-elf/ChangeLog
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@@ -1,3 +1,10 @@
Fri Dec 5 10:11:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.
* t-trap.s: New file.
* Makefile.in (TESTS): Update.
Thu Dec 4 16:56:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-macros.i: Add definitions for PSW bits.