sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.

sim/configure

@@ -690,6 +690,7 @@ moxie
 msp430
 or1k
 pru
+riscv
 rl78
 rx
 sh
@@ -4028,6 +4029,13 @@ subdirs="$subdirs aarch64"
   subdirs="$subdirs pru"
 
 
+       ;;
+   riscv*-*-*)
+
+  sim_arch=riscv
+  subdirs="$subdirs riscv"
+
+
        ;;
    rl78-*-*)