sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.

sim/common/gennltvals.py

@@ -50,6 +50,7 @@ TARGET_DIRS = {
     'd10v': 'newlib/libc/sys/d10v/sys',
     'i960': 'libgloss/i960',
     'mcore': 'libgloss/mcore',
+    'riscv': 'libgloss/riscv/machine',
     'v850': 'libgloss/v850/sys',
 }
 TARGETS = {
@@ -66,6 +67,7 @@ TARGETS = {
     'mn10300',
     'msp430',
     'pru',
+    'riscv',
     'sparc',
     'v850',
 }