forked from Imagelibrary/binutils-gdb
Add MIPS r3 and r5 support.
This patch firstly adds support for mips32r3 mips32r5, mips64r3 and mips64r5. Secondly it adds support for the eretnc instruction. ChangeLog: bfd/ * aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3, mips32r5 and mips64r5. * archures.c (bfd_architecture): Likewise. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (arch_info_struct): Likewise. * elfxx-mips.c (mips_set_isa_flags): Likewise. gas/ * tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3 and mips64r5. (ISA_HAS_64BIT_FPRS): Likewise. (ISA_HAS_ROR): Likewise. (ISA_HAS_ODD_SINGLE_FPR): Likewise. (ISA_HAS_MXHC1): Likewise. (hilo_interlocks): Likewise. (md_longopts): Likewise. (ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5. (ISA_HAS_DROR): Likewise. (options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and OPTION_MIPS64R5. (mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and mips64r5. (md_parse_option): Likewise. (s_mipsset): Likewise. (mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3 and mips64r5. Also change p5600 entry to be mips32r5. * configure.in: Add support for mips32r3, mips32r5, mips64r3 and mips64r5. * configure: Regenerate. * doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and -mips64r5 command line options. * doc/as.texinfo: Likewise. gas/testsuite/ * gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3, mips32r5, mips64r3 and mips64r5 isas to the testsuite. * gas/mips/r5.s: New test. * gas/mips/r5.d: Likewise. include/opcode/ * mips.h (INSN_ISA_MASK): Updated. (INSN_ISA32R3): New define. (INSN_ISA32R5): New define. (INSN_ISA64R3): New define. (INSN_ISA64R5): New define. (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and mips64r5. (INSN_UPTO32R3): New define. (INSN_UPTO32R5): New define. (INSN_UPTO64R3): New define. (INSN_UPTO64R5): New define. (ISA_MIPS32R3): New define. (ISA_MIPS32R5): New define. (ISA_MIPS64R3): New define. (ISA_MIPS64R5): New define. (CPU_MIPS32R3): New define. (CPU_MIPS32R5): New define. (CPU_MIPS64R3): New define. (CPU_MIPS64R5): New define. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction. (I34): New define. (I36): New define. (I66): New define. (I68): New define. * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and mips64r5. (parse_mips_dis_option): Update MSA and virtualization support to allow mips64r3 and mips64r5.
This commit is contained in:
Andrew Bennett
@@ -1,3 +1,27 @@
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2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips.h (INSN_ISA_MASK): Updated.
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(INSN_ISA32R3): New define.
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(INSN_ISA32R5): New define.
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(INSN_ISA64R3): New define.
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(INSN_ISA64R5): New define.
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(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
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INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
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(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
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mips64r5.
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(INSN_UPTO32R3): New define.
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(INSN_UPTO32R5): New define.
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(INSN_UPTO64R3): New define.
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(INSN_UPTO64R5): New define.
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(ISA_MIPS32R3): New define.
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(ISA_MIPS32R5): New define.
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(ISA_MIPS64R3): New define.
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(ISA_MIPS64R5): New define.
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(CPU_MIPS32R3): New define.
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(CPU_MIPS32R5): New define.
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(CPU_MIPS64R3): New define.
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(CPU_MIPS64R5): New define.
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2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
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@@ -1058,7 +1058,7 @@ struct mips_opcode
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word constructed using these macros is a bitmask of the remaining
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INSN_* values below. */
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#define INSN_ISA_MASK 0x0000000ful
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#define INSN_ISA_MASK 0x0000001ful
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/* We cannot start at zero due to ISA_UNKNOWN below. */
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#define INSN_ISA1 1
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@@ -1068,17 +1068,21 @@ struct mips_opcode
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#define INSN_ISA5 5
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#define INSN_ISA32 6
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#define INSN_ISA32R2 7
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#define INSN_ISA64 8
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#define INSN_ISA64R2 9
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#define INSN_ISA32R3 8
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#define INSN_ISA32R5 9
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#define INSN_ISA64 11
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#define INSN_ISA64R2 12
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#define INSN_ISA64R3 13
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#define INSN_ISA64R5 14
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/* Below this point the INSN_* values correspond to combinations of ISAs.
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They are only for use in the opcodes table to indicate membership of
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a combination of ISAs that cannot be expressed using the usual inclusion
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ordering on the above INSN_* values. */
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#define INSN_ISA3_32 10
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#define INSN_ISA3_32R2 11
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#define INSN_ISA4_32 12
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#define INSN_ISA4_32R2 13
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#define INSN_ISA5_32R2 14
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#define INSN_ISA3_32 16
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#define INSN_ISA3_32R2 17
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#define INSN_ISA4_32 18
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#define INSN_ISA4_32R2 19
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#define INSN_ISA5_32R2 20
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/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
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#define ISAF(X) (1 << (INSN_ISA##X - 1))
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@@ -1090,8 +1094,12 @@ struct mips_opcode
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#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
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#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
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| ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
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#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
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#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
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#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
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#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
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#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
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#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
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/* The same information in table form: bit INSN_ISA<X> - 1 of index
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INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
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@@ -1103,8 +1111,13 @@ static const unsigned int mips_isa_table[] = {
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INSN_UPTO5,
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INSN_UPTO32,
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INSN_UPTO32R2,
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INSN_UPTO32R3,
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INSN_UPTO32R5,
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0,
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INSN_UPTO64,
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INSN_UPTO64R2
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INSN_UPTO64R2,
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INSN_UPTO64R3,
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INSN_UPTO64R5
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};
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#undef ISAF
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@@ -1188,7 +1201,11 @@ static const unsigned int mips_isa_table[] = {
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#define ISA_MIPS64 INSN_ISA64
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#define ISA_MIPS32R2 INSN_ISA32R2
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#define ISA_MIPS32R3 INSN_ISA32R3
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#define ISA_MIPS32R5 INSN_ISA32R5
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#define ISA_MIPS64R2 INSN_ISA64R2
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#define ISA_MIPS64R3 INSN_ISA64R3
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#define ISA_MIPS64R5 INSN_ISA64R5
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/* CPU defines, use instead of hardcoding processor number. Keep this
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@@ -1220,9 +1237,13 @@ static const unsigned int mips_isa_table[] = {
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#define CPU_MIPS16 16
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#define CPU_MIPS32 32
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#define CPU_MIPS32R2 33
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#define CPU_MIPS32R3 34
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#define CPU_MIPS32R5 36
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#define CPU_MIPS5 5
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#define CPU_MIPS64 64
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#define CPU_MIPS64R2 65
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#define CPU_MIPS64R3 66
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#define CPU_MIPS64R5 68
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#define CPU_SB1 12310201 /* octal 'SB', 01. */
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#define CPU_LOONGSON_2E 3001
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#define CPU_LOONGSON_2F 3002
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