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2000-08-04 Kazu Hirata <kazu@hxi.com>

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* config/tc-cris.c: Rearrange code for readability.
	* config/tc-d10v.c: Fix formatting.
	* config/tc-m32r.c: Likewise.
	* config/tc-sparc.c: Likewise.
This commit is contained in:
Kazu Hirata
2000-08-04 01:01:32 +00:00
parent dcb5e6e634
commit ab3e48dc5d
5 changed files with 421 additions and 389 deletions
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7
gas/ChangeLog
View File

@@ -1,3 +1,10 @@
2000-08-04 Kazu Hirata <kazu@hxi.com>
* config/tc-cris.c: Rearrange code for readability.
* config/tc-d10v.c: Fix formatting.
* config/tc-m32r.c: Likewise.
* config/tc-sparc.c: Likewise.
2000-08-02 Jim Wilson <wilson@cygnus.com>
* config/tc-ia64.c (emit_one_bundle): Call ia64_free_opcode

38
gas/config/tc-cris.c
View File

@@ -1760,10 +1760,9 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
We break out to check the final ']'. */
break;
}
else
/* It wasn't an idirection. Check if it's a
/* It wasn't an indirection. Check if it's a
register. */
if (get_gen_reg (cPP, &index_reg_number))
else if (get_gen_reg (cPP, &index_reg_number))
{
int size_bits;
@@ -1784,9 +1783,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
break;
}
}
else
/* Not a register. Then this must be "[rN+I]". */
if (cris_get_expression (cPP, &prefixp->expr))
else if (cris_get_expression (cPP, &prefixp->expr))
{
/* We've got offset with assign mode. Fill
in the blanks and break out to match the
@@ -1799,9 +1797,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
this can't be a match. */
return 0;
}
else
/* Not "[rN+" but perhaps "[rN-"? */
if (**cPP == '-')
else if (**cPP == '-')
{
/* We must have an offset with assign mode. */
if (! cris_get_expression (cPP, &prefixp->expr))
@@ -1838,9 +1835,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
return 1;
}
}
else
/* No indirection. Perhaps a constant? */
if (cris_get_expression (cPP, imm_exprP))
else if (cris_get_expression (cPP, imm_exprP))
{
/* Expression found, this is immediate mode. */
prefixp->kind = PREFIX_NONE;
@@ -1873,12 +1869,11 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
char **cPP;
struct cris_prefix *prefixp;
{
int reg_number;
if (**cPP != '[')
/* We must have a '[' or it's a clean failure. */
return 0;
else
{
int reg_number;
/* Eat the first '['. */
(*cPP)++;
@@ -1915,10 +1910,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
/* Eat the first ']', so we'll be looking at a second ']'. */
(*cPP)++;
}
else
/* No second '['. Then we should have a register here, making
it "[rN". */
if (get_gen_reg (cPP, &prefixp->base_reg_number))
else if (get_gen_reg (cPP, &prefixp->base_reg_number))
{
/* This must be indexed or offset mode: "[rN+I]" or
"[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */
@@ -1973,10 +1967,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
expect a final ']', which we'll do in a common
closing session. */
}
else
/* Seen "[rN+", but not a '[', so check if we have a
register. */
if (get_gen_reg (cPP, &index_reg_number))
else if (get_gen_reg (cPP, &index_reg_number))
{
/* This is indexed mode: "[rN+rM.S]" or
"[rN+rM.S+]". */
@@ -1996,10 +1989,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
the common checking of the closing ']'. */
prefixp->opcode |= size_bits << 4;
}
else
/* Seen "[rN+", but not a '[' or a register, so then
it must be a constant "I". */
if (cris_get_expression (cPP, &prefixp->expr))
else if (cris_get_expression (cPP, &prefixp->expr))
{
/* Expression found, so fill in the bits of offset
mode and drop down to check the closing ']'. */
@@ -2009,9 +2001,8 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
/* Nothing valid here: lose. */
return 0;
}
else
/* Seen "[rN" but no '+', so check if it's a '-'. */
if (**cPP == '-')
else if (**cPP == '-')
{
/* Yep, we must have offset mode. */
if (! cris_get_expression (cPP, &prefixp->expr))
@@ -2042,12 +2033,10 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
prefixp->kind = PREFIX_BDAP_IMM;
}
}
else
{
/* A '[', but no second '[', and no register. Check if we
have an expression, making this "[I]" for a double-indirect
prefix. */
if (cris_get_expression (cPP, &prefixp->expr))
else if (cris_get_expression (cPP, &prefixp->expr))
{
/* Expression found, the so called absolute mode for a
double-indirect prefix on PC. */
@@ -2059,8 +2048,6 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
else
/* Neither '[' nor register nor expression. We lose. */
return 0;
}
}
/* We get here as a closing ceremony to a successful match. We just
need to check the closing ']'. */
@@ -2780,7 +2767,6 @@ tc_cris_check_adjusted_broken_word (new_offset, brokwP)
(long) new_offset);
}
/*
* Local variables:
* eval: (c-set-style "gnu")

4
gas/config/tc-d10v.c
View File

@@ -100,6 +100,7 @@ struct option md_longopts[] =
{"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
static void d10v_dot_word PARAMS ((int));
@@ -547,7 +548,8 @@ d10v_insert_operand (insn, op_type, value, left, fix)
/* Truncate to the proper number of bits. */
if (check_range (value, bits, d10v_operands[op_type].flags))
as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value);
as_bad_where (fix->fx_file, fix->fx_line,
_("operand out of range: %d"), value);
value &= 0x7FFFFFFF >> (31 - bits);
insn |= (value << shift);

133
gas/config/tc-m32r.c
View File

@@ -1,5 +1,6 @@
/* tc-m32r.c -- Assembler for the Mitsubishi M32R.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
Copyright (C) 1996, 1997, 1998, 1999, 2000
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
@@ -74,7 +75,8 @@ static int seen_relaxable_p = 0;
This flag does not apply to them. */
static int m32r_relax;
#if 0 /* not supported yet */
#if 0
/* Not supported yet. */
/* If non-NULL, pointer to cpu description file to read.
This allows runtime additions to the assembler. */
static const char *m32r_cpu_desc;
@@ -106,7 +108,7 @@ static int warn_explicit_parallel_conflicts = 1;
/* Non-zero if insns can be made parallel. */
static int optimize;
/* stuff for .scomm symbols. */
/* Stuff for .scomm symbols. */
static segT sbss_section;
static asection scom_section;
static asymbol scom_symbol;
@@ -130,16 +132,19 @@ const char FLT_CHARS[] = "dD";
struct m32r_hi_fixup
{
struct m32r_hi_fixup * next; /* Next HI fixup. */
fixS * fixp; /* This fixup. */
segT seg; /* The section this fixup is in. */
/* Next HI fixup. */
struct m32r_hi_fixup *next;
/* This fixup. */
fixS *fixp;
/* The section this fixup is in. */
segT seg;
};
/* The list of unmatched HI relocs. */
static struct m32r_hi_fixup *m32r_hi_fixup_list;
static void
allow_m32rx (on)
@@ -153,6 +158,7 @@ allow_m32rx (on)
}
#define M32R_SHORTOPTS "O"
const char *md_shortopts = M32R_SHORTOPTS;
struct option md_longopts[] =
@@ -177,7 +183,8 @@ struct option md_longopts[] =
{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
#if 0 /* not supported yet */
#if 0
/* Not supported yet. */
#define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
#define OPTION_CPU_DESC (OPTION_RELAX + 1)
{"relax", no_argument, NULL, OPTION_RELAX},
@@ -185,6 +192,7 @@ struct option md_longopts[] =
#endif
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
int
@@ -233,7 +241,8 @@ md_parse_option (c, arg)
warn_unmatched_high = 0;
break;
#if 0 /* not supported yet */
#if 0
/* Not supported yet. */
case OPTION_RELAX:
m32r_relax = 1;
break;
@@ -316,7 +325,7 @@ const pseudo_typeS md_pseudo_table[] =
/* FIXME: Should be machine generated. */
#define NOP_INSN 0x7000
#define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
/* When we align the .text section, insert the correct NOP pattern.
N is the power of 2 alignment. LEN is the length of pattern FILL.
@@ -510,7 +519,8 @@ md_begin ()
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
#if 0 /* not supported yet */
#if 0
/* Not supported yet. */
/* If a runtime cpu description file was provided, parse it. */
if (m32r_cpu_desc != NULL)
{
@@ -534,7 +544,8 @@ md_begin ()
applicable = bfd_applicable_section_flags (stdoutput);
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
#if 0 /* What does this do? [see perform_an_assembly_pass] */
#if 0
/* What does this do? [see perform_an_assembly_pass] */
seg_info (bss_section)->bss = 1;
#endif
@@ -642,7 +653,8 @@ static int
writes_to_pc (a)
m32r_insn *a;
{
#if 0 /* Once PC operands are working.... */
#if 0
/* Once PC operands are working.... */
const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
a->insn);
@@ -652,7 +664,8 @@ writes_to_pc (a)
while (a_operands->type != CGEN_OPINST_END)
{
if (a_operands->operand != NULL
&& CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC)
&& CGEN_OPERAND_INDEX (gas_cgen_cpu_desc,
a_operands->operand) == M32R_OPERAND_PC)
return 1;
a_operands++;
@@ -665,8 +678,8 @@ writes_to_pc (a)
return 0;
}
/* Returns NULL if the two 16 bit insns can be executed in parallel,
otherwise it returns a pointer to an error message explaining why not. */
/* Return NULL if the two 16 bit insns can be executed in parallel.
Otherwise return a pointer to an error message explaining why not. */
static const char *
can_make_parallel (a, b)
@@ -741,7 +754,8 @@ assemble_two_insns (str, str2, parallel_p)
char *errmsg;
char save_str2 = *str2;
* str2 = 0; /* Seperate the two instructions. */
/* Seperate the two instructions. */
*str2 = 0;
/* Make sure the two insns begin on a 32 bit boundary.
This is also done for the serial case (foo -> bar), relaxing doesn't
@@ -778,7 +792,8 @@ assemble_two_insns (str, str2, parallel_p)
}
else if (! enable_m32rx
/* FIXME: Need standard macro to perform this test. */
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
&& (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
== (1 << MACH_M32RX)))
{
/* xgettext:c-format */
as_bad (_("instruction '%s' is for the M32RX only"), str);
@@ -786,17 +801,26 @@ assemble_two_insns (str, str2, parallel_p)
}
/* Check to see if this is an allowable parallel insn. */
if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
if (parallel_p
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
return;
}
*str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
str3 = str; /* Save the original string pointer. */
str = str2 + 2; /* Advanced past the parsed string. */
str2 = str3; /* Remember the entire string in case it is needed for error messages. */
/* Restore the original assembly text, just in case it is needed. */
*str2 = save_str2;
/* Save the original string pointer. */
str3 = str;
/* Advanced past the parsed string. */
str = str2 + 2;
/* Remember the entire string in case it is needed for error
messages. */
str2 = str3;
/* Convert the opcode to lower case. */
{
@@ -815,7 +839,8 @@ assemble_two_insns (str, str2, parallel_p)
}
}
/* Preserve any fixups that have been generated and reset the list to empty. */
/* Preserve any fixups that have been generated and reset the list
to empty. */
gas_cgen_save_fixups ();
/* Get the indices of the operands of the instruction. */
@@ -871,7 +896,8 @@ assemble_two_insns (str, str2, parallel_p)
}
/* Check to see if this is an allowable parallel insn. */
if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
if (parallel_p
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
@@ -1093,8 +1119,7 @@ md_assemble (str)
&& optimize
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
&& ! writes_to_pc (&prev_insn)
&& ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
)
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
{
if (can_make_parallel (&prev_insn, &insn) == NULL)
make_parallel (insn.buffer);
@@ -1207,9 +1232,9 @@ md_undefined_symbol (name)
/* .scomm pseudo-op handler.
This is a new pseudo-op to handle putting objects in .scommon.
By doing this the linker won't need to do any work and more importantly
it removes the implicit -G arg necessary to correctly link the object file.
*/
By doing this the linker won't need to do any work,
and more importantly it removes the implicit -G arg necessary to
correctly link the object file. */
static void
m32r_scomm (ignore)
@@ -1226,7 +1251,7 @@ m32r_scomm (ignore)
name = input_line_pointer;
c = get_symbol_end ();
/* just after name is now '\0' */
/* Just after name is now '\0'. */
p = input_line_pointer;
*p = c;
SKIP_WHITESPACE ();
@@ -1237,7 +1262,8 @@ m32r_scomm (ignore)
return;
}
input_line_pointer ++; /* skip ',' */
/* Skip ','. */
input_line_pointer++;
if ((size = get_absolute_expression ()) < 0)
{
/* xgettext:c-format */
@@ -1259,6 +1285,7 @@ m32r_scomm (ignore)
align = 8;
}
}
/* Convert to a power of 2 alignment. */
if (align)
{
@@ -1414,8 +1441,8 @@ m32r_relax_frag (fragP, stretch)
Any symbol that is now undefined will not become defined.
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
Although it may not be explicit in the frag, pretend fr_var starts with a
0 value. */
Although it may not be explicit in the frag, pretend fr_var starts
with a 0 value. */
int
md_estimate_size_before_relax (fragP, segment)
@@ -1437,7 +1464,8 @@ md_estimate_size_before_relax (fragP, segment)
all further handling to md_convert_frag. */
fragP->fr_subtype = 2;
#if 0 /* Can't use this, but leave in for illustration. */
#if 0
/* Can't use this, but leave in for illustration. */
/* Change 16 bit insn to 32 bit insn. */
fragP->fr_opcode[0] |= 0x80;
@@ -1483,7 +1511,7 @@ md_estimate_size_before_relax (fragP, segment)
return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
}
/* *fragP has been relaxed to its final size, and now needs to have
/* *FRAGP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size.
Called after relaxation is finished.
@@ -1532,7 +1560,7 @@ md_convert_frag (abfd, sec, fragP)
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
{
/* symbol must be resolved by linker */
/* Symbol must be resolved by linker. */
if (fragP->fr_offset & 3)
as_warn (_("Addend to unresolved symbol not on word boundary."));
addend = fragP->fr_offset >> 2;
@@ -1556,8 +1584,8 @@ md_convert_frag (abfd, sec, fragP)
/* Offset of branch insn in frag. */
fragP->fr_fix + extension - 4,
fragP->fr_cgen.insn,
4 /*length*/,
/* FIXME: quick hack */
4 /* Length. */,
/* FIXME: quick hack. */
#if 0
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
fragP->fr_cgen.opindex),
@@ -1622,7 +1650,8 @@ md_cgen_lookup_reloc (insn, operand, fixP)
if (fixP->fx_cgen.opinfo != 0)
return fixP->fx_cgen.opinfo;
break;
default : /* avoid -Wall warning */
default:
/* Avoid -Wall warning. */
break;
}
return BFD_RELOC_NONE;
@@ -1674,7 +1703,8 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
|| fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
break;
default : /* avoid -Wall warning */
default:
/* Avoid -Wall warning */
break;
}
@@ -1783,8 +1813,7 @@ m32r_force_relocation (fix)
if (! m32r_relax)
return 0;
return (fix->fx_pcrel
|| 0 /* ??? */);
return fix->fx_pcrel;
}
/* Write a value out to the object file, using the appropriate endianness. */
@@ -1801,12 +1830,12 @@ md_number_to_chars (buf, val, n)
number_to_chars_littleendian (buf, val, n);
}
/* Turn a string in input_line_pointer into a floating point constant of type
type, and store the appropriate bytes in *litP. The number of LITTLENUMS
emitted is stored in *sizeP . An error message is returned, or NULL on OK.
*/
/* Turn a string in input_line_pointer into a floating point constant
of type TYPE, and store the appropriate bytes in *LITP. The number
of LITTLENUMS emitted is stored in *SIZEP. An error message is
returned, or NULL on OK. */
/* Equal to MAX_PRECISION in atof-ieee.c */
/* Equal to MAX_PRECISION in atof-ieee.c. */
#define MAX_LITTLENUMS 6
char *
@@ -1837,7 +1866,8 @@ md_atof (type, litP, sizeP)
prec = 4;
break;
/* FIXME: Some targets allow other format chars for bigger sizes here. */
/* FIXME: Some targets allow other format chars for bigger sizes
here. */
default:
*sizeP = 0;
@@ -1896,7 +1926,8 @@ m32r_fix_adjustable (fixP)
{
const CGEN_INSN *insn = NULL;
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
const CGEN_OPERAND *operand =
cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
}
else
@@ -1911,7 +1942,7 @@ m32r_fix_adjustable (fixP)
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
/* We need the symbol name for the VTABLE entries */
/* We need the symbol name for the VTABLE entries. */
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
return 0;

38
gas/config/tc-sparc.c
View File

@@ -301,7 +301,8 @@ sparc_target_format ()
return "a.out-sunos-big";
else if (default_arch_type == sparc86x && target_little_endian_data)
return "a.out-sunos-big";
else return "a.out-sparc-little";
else
return "a.out-sparc-little";
#else
return "a.out-sunos-big";
#endif
@@ -785,8 +786,9 @@ md_begin ()
for (i = 0; native_op_table[i].name; i++)
{
const struct sparc_opcode *insn;
char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
native_op_table[i].name64;
char *name = sparc_arch_size == (32
? native_op_table[i].name32
: native_op_table[i].name64);
insn = (struct sparc_opcode *) hash_find (op_hash, name);
if (insn == NULL)
{
@@ -1005,10 +1007,10 @@ synthetize_setuw (insn)
{
the_insn.opcode = (SETHI_INSN | RD (rd)
| ((the_insn.exp.X_add_number >> 10)
& (the_insn.exp.X_op == O_constant ? 0x3fffff : 0)));
& (the_insn.exp.X_op == O_constant
? 0x3fffff : 0)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_HI22
: BFD_RELOC_NONE);
? BFD_RELOC_HI22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
need_hi22_p = 1;
}
@@ -1021,11 +1023,10 @@ synthetize_setuw (insn)
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
| RD (rd) | IMMED
| (the_insn.exp.X_add_number
& (the_insn.exp.X_op != O_constant ? 0 :
need_hi22_p ? 0x3ff : 0x1fff)));
& (the_insn.exp.X_op != O_constant
? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_LO10
: BFD_RELOC_NONE);
? BFD_RELOC_LO10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
}
@@ -1122,7 +1123,8 @@ synthetize_setx (insn)
return;
}
need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
lower32 = 0; upper32 = 0;
lower32 = 0;
upper32 = 0;
}
else
{
@@ -2029,7 +2031,7 @@ sparc_ip (str, pinsn)
case 'J':
opcode |= RD (mask);
continue;
} /* pack it in. */
} /* Pack it in. */
know (0);
break;
@@ -2772,7 +2774,8 @@ md_atof (type, litP, sizeP)
{
for (i = 0; i < prec; i++)
{
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
@@ -2780,7 +2783,8 @@ md_atof (type, litP, sizeP)
{
for (i = prec - 1; i >= 0; i--)
{
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
@@ -3355,7 +3359,8 @@ tc_gen_reloc (section, fixp)
relocs[2] = NULL;
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section));
*reloc->sym_ptr_ptr
= symbol_get_bfdsym (section_symbol (absolute_section));
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
reloc->addend = fixp->tc_fix_data;
@@ -4033,7 +4038,8 @@ sparc_handle_align (fragp)
as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
{
int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
int count =
fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
if (count >= 4
&& !(count & 3)