From aae8784c58d693fa8bc0161b325fc8bcd76d18fc Mon Sep 17 00:00:00 2001 From: changjiachen Date: Thu, 28 Dec 2023 20:07:54 +0800 Subject: [PATCH] LoongArch: bfd: Add support for tls le relax. Add tls le relax support and related relocs in bfd. New relocation related explanation can refer to the following url: https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc This support does two main things: 1. Implement support for three new relocation items in bfd. The three new relocation items are shown below: R_LARCH_TLS_LE_ADD_R R_LARCH_TLS_LE_HI20_R R_LARCH_TLS_LE_LO12_R 2. ADD a new macro RELOCATE_TLS_TP32_HI20 Handle problems caused by symbol extensions in TLS LE, The processing is similar to the macro RELOCATE_CALC_PC32_HI20 method. 3. Implement the tls le relax function. bfd/ChangeLog: * bfd-in2.h: Add relocs related to tls le relax. * elfnn-loongarch.c: (loongarch_relax_tls_le): New function. (RELOCATE_TLS_TP32_HI20): New macro. (loongarch_elf_check_relocs): Add new reloc support. (perform_relocation): Likewise. (loongarch_elf_relocate_section): Handle new relocs related to relax. (loongarch_elf_relax_section): Likewise. * elfxx-loongarch.c: (LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise. * libbfd.h: Add relocs related to tls le relax. * reloc.c: Likewise. --- bfd/.elfnn-loongarch.c.swp | Bin 0 -> 16384 bytes bfd/bfd-in2.h | 4 ++ bfd/elfnn-loongarch.c | 105 +++++++++++++++++++++++++++++++++++++ bfd/elfxx-loongarch.c | 55 +++++++++++++++++-- bfd/libbfd.h | 3 ++ bfd/reloc.c | 7 +++ 6 files changed, 169 insertions(+), 5 deletions(-) create mode 100644 bfd/.elfnn-loongarch.c.swp diff --git a/bfd/.elfnn-loongarch.c.swp b/bfd/.elfnn-loongarch.c.swp new file mode 100644 index 0000000000000000000000000000000000000000..74539aabdd73056a3e5bed1cfa9c166afc362545 GIT binary patch literal 16384 zcmeHOU5q4E6>eNWM_E8HnuyBT-MCB-)AP50u)_}Y&h*T7=;;}{d)OVt6xG$$-L+F) z)mv3PKd_4+5=nGPj1U$R!%rk88u0;N6%0i50YiL15J3Ra3L@ z;)A9;`L=uRch9-!p8Heho?BZUxgtAD7Y&Uh@Hst^cp-aOfAPqxC!GH9NJ6WtR&Bqb zYIWUWdZSOVWz|(<&9-VA)$q%&?N&JK*|v!S!y0xSZMbY$EzdCBRIO4TE>|nVx>>cX zlxah&>S*;L?fANTY|jHd54@iTHYawBjf$ndZR-{~^NfY}6X@|h5A;0H^FYr7JrDFe z(DOjg13eG)Jn(-A=#%D`F%p<`#t$tmF2;AQ19Q859E(U#2E z8z+Y4-<14yl0O#V-;lg3`Q}Ms`M*cxpNsIXOa2-uubmv0e@*f&$v++8UyaBYKOB}n zCi!cn{I4VYE0Pb!J@=8Y{L7LL#`mEJ|B~bzQvXC>SpG%HACUYHBmCbY{AWHImVZI= zo|Hcv;g3o_m>(y6EG++5$p_bpO(BK<*z_4 zkw3xudP?$Dzc_J!g#W$dP04@$_4ZT5te^K^2<{G#t8qo zzoe2M1$p`*lIWw&PG06w>>x~F6x0A%BQvcc~!t%1X_to=2&jURV^gPh>K+gj` z5A;0H^T2=A11bW3J}SS-fi`0DAb$Q0;`<}ODzE}v0GtoJgmc9`z*WFSz=gmYIIG+T zIKXZo4ZMr<&jY}%z%9VFz7*!1=)0Kp*fr&W}$44*?GX-vu;)&z&a%uj71r40r{27`O%aHedq{ zU>=wQ&IUFC3E(}Pi5~-w0Ji}ukOcaHS8(2b47eNMvw0cV1)K~#i?jSsfct=(fo}r) z0RtEV&H_FSJbz*$@hjk$z;}S_fjUqFE(Fd7J_j7dVd8$^d%#`5oxlQcF7P4-^GCql zz+J#0;2Y%ayk^T&Q05u7m6}*?sB|ucNxNEgb+1d+ zY&O48ROa#-sKL7*3WSn0LMa+WB_cGOU&!T>{PPlS$#YtoN9}h*6uc{7%C^~QKu!x3 zD;mGE#1;HsQdzN~nx<3*jy!nVw-UW;HVvyrLa=QzTr4_418!x_^4N2Ms=DoXDXrzX ztfj_-Z4>IK4MPh?d7THOfpN1HW#fr!5+7t{ixshbJFyzOydM^dX^e4-nYUui$jZWg z;sutZExW{$67$tx89dJDhf+1wWxM6bdRPcdc&fu3Hz|2B&w~|VxJqbIh&BS<7-4*N z(sqS4h3eri469PJJ;gI!#anCY)UUFEU&8oUmDMjNMF)7evm=tp_DpIvJ>#+E>XFkq1CgFJs=LsDo&FZ$zz#A@pLG_XmH`cAA+hDWzOdnVCw`!Gjb}Wr~ws&2~hTbbe8pZ_6Y}Ovd)#5%pM^@zjRu zch8mfMD({i-?0MXGQ3bW}P(P*f2A%9tZZf~AO zc-*?iJ~~z(Y=;x$%FoZ-hR@CJ*>(tRI=a_#EPv-#nx2CvzP*CoSZ;CS3EmR=`iS@m zoX;x-rL;JYNTcF6sbdyP*1Y+;+*02k6T)uuPwmye9D8;iCzX7p`1~I99?c4zN z$E@Y)j)jF(z|#~DZ5M$~M-4yX+Zy;Ot%{A726zn*l8O@aj|SSd4C0xfdU&Xm@wzO6 zFT>KzRz;_+c2lz}`fywIPUUTR0@XE@{P|a!$*-mZPG&J3E zb$56o2x}01V326V@DNkg5d$?HyXL5kaiN1_u&RN0aB^;bF`J*+0kLeAEZZC8W)|%h zxpli`RuGge>zGWMZY(3_P)W0!YaGw81_T|5=q%kq5HjB?!wAaxh6rOfrp0!NKnG!$ z?x}dcd5Bw`%^>Vf=S%6`*<7}?NZ3-Rv!#5dSfuH>0;Op_T_|NI7Z8Ke{6b-Vu9$(@ zMYsgUu!3^SqrKVEp1Fk*VZ))l=|Tbe7RQAf5P^}tjF^y3HyTaTK!;XT$5AbhyTlqw zU7q5=v0`BD8qkZXhA&yS@i_MCDgsLndJ#I6b!xeKwPg;9Zuf&)<5h|V=c||uJX&sDM3Hg*uCigSG;Ex^gMGllJm@%t+g7d0Fh;3iSB&bK=)7>Cm{~mK zRL5g`c27?Y3JZ4|mWt41nrGgW?rM(F^dOJr;h=m-XqdDSzDSoN#1%W9Yg?4_D#CA* zn1GH^t9#TxnWV9ivC$O%*|DK72Ptc5L!r$x-b#QQ%&H?*gv_f?U7^eqRiX125zJeyNMP|B*dq+1oG;vxQ2^i>gJx=PdZ z5bU?3eZ+Ab1|x*#UmUxx26?_{pxn*1<-1!FCo`O{k-!m&jCL4%!Fhgq$me2ZYmU97 zG+mJ`Ys-lMy^A@Hq{9()%Z=FV%StX*8tzbFma>c>Fx+kz6DwKMl!odcJ!#uZ5z%fc zR#v8Xni0967%@%Q7UXpi?q&S01yDewp0m|BokAH}FTi>iDWS z4ad#9s2%>i=(NjL#MX(`hM9@9lBWlKk2okw$Les6tMzq0j3|n&6RXY7!*=w=^)I$g ztTv=JwIyDEwicbl-PF37p*cExE zcOoIEXr}6R_cKayEbVVgowgb}@|8-{F_yWr|vph_UGYb}ZFjh-_{vcig=MqPO?ebmJYC8yOji(35+z z`HV6-Hb2q_LWp_2u 0x7ff) \ + relocation += 0x800; \ + relocation = relocation & ~(bfd_vma)0xfff; \ + }) + /* For example: pc is 0x11000010000100, symbol is 0x1812348ffff812 offset = (0x1812348ffff812 & ~0xfff) - (0x11000010000100 & ~0xfff) = 0x712347ffff000 @@ -3481,6 +3495,13 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, break; + case R_LARCH_TLS_LE_HI20_R: + relocation -= elf_hash_table (info)->tls_sec->vma; + + RELOCATE_TLS_TP32_HI20 (relocation); + + break; + case R_LARCH_PCALA_LO12: /* Not support if sym_addr in 2k page edge. pcalau12i pc_hi20 (sym_addr) @@ -3651,6 +3672,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, case R_LARCH_TLS_LE_HI20: case R_LARCH_TLS_LE_LO12: + case R_LARCH_TLS_LE_LO12_R: case R_LARCH_TLS_LE64_LO20: case R_LARCH_TLS_LE64_HI12: BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); @@ -4089,6 +4111,82 @@ loongarch_relax_delete_bytes (bfd *abfd, return true; } +/* Relax tls le, mainly relax the process of getting TLS le symbolic addresses. + there are three situations in which an assembly instruction sequence needs to + be relaxed: + symbol address = tp + offset (symbol),offset (symbol) = le_hi20_r + le_lo12_r + + Case 1: + in this case, the rd register in the st.{w/d} instruction does not store the + full tls symbolic address, but tp + le_hi20_r, which is a part of the tls + symbolic address, and then obtains the rd + le_lo12_r address through the + st.w instruction feature. + this is the full tls symbolic address (tp + le_hi20_r + le_lo12_r). + + before relax: after relax: + + lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) + add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) + st.{w/d} $rs,$rd,%le_lo12_r (sym) ==> st.{w/d} $rs,$tp,%le_lo12_r (sym) + + Case 2: + in this case, ld.{w/d} is similar to st.{w/d} in case1. + + before relax: after relax: + + lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) + add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) + ld.{w/d} $rs,$rd,%le_lo12_r (sym) ==> ld.{w/d} $rs,$tp,%le_lo12_r (sym) + + Case 3: + in this case,the rs register in addi.{w/d} stores the full address of the tls + symbol (tp + le_hi20_r + le_lo12_r). + + before relax: after relax: + + lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) + add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) + addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym) +*/ +static bool +loongarch_relax_tls_le (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel, + struct bfd_link_info *link_info, + bfd_vma symval) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); + static uint32_t insn_rj,insn_rd; + symval = symval - elf_hash_table (link_info)->tls_sec->vma; + /* Whether the symbol offset is in the interval (offset < 0x800). */ + if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800)) + { + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_TLS_LE_ADD_R: + /* delete insn. */ + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info); + break; + case R_LARCH_TLS_LE_LO12_R: + /* Change rj to $tp. */ + insn_rj = 0x2 << 5; + /* Get rd register. */ + insn_rd = insn & 0x1f; + /* Write symbol offset. */ + symval <<= 10; + /* Writes the modified instruction. */ + insn = insn & 0xffc00000; + insn = insn | symval | insn_rj | insn_rd; + bfd_put (32, abfd, insn, contents + rel->r_offset); + break; + default: + break; + } + } + return true; +} /* Relax pcalau12i,addi.d => pcaddi. */ static bool @@ -4518,6 +4616,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); } break; + case R_LARCH_TLS_LE_HI20_R: + case R_LARCH_TLS_LE_LO12_R: + case R_LARCH_TLS_LE_ADD_R: + if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) + loongarch_relax_tls_le (abfd, sec, rel, info, symval); + break; + case R_LARCH_PCALA_HI20: if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c index 4fe8cbff14c..2c40fb02872 100644 --- a/bfd/elfxx-loongarch.c +++ b/bfd/elfxx-loongarch.c @@ -1776,9 +1776,56 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = NULL, /* adjust_reloc_bits. */ "desc_call"), /* larch_reloc_type_name. */ - LOONGARCH_EMPTY_HOWTO (121), - LOONGARCH_EMPTY_HOWTO (122), - LOONGARCH_EMPTY_HOWTO (123), + LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R, /* type (121). */ + 12, /* rightshift. */ + 4, /* size. */ + 20, /* bitsize. */ + false, /* pc_relative. */ + 5, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_TLS_LE_HI20_R", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x1ffffe0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_TLS_LE_HI20_R, /* bfd_reloc_code_real_type. */ + reloc_bits, /* adjust_reloc_bits. */ + "le_hi20_r"), /* larch_reloc_type_name. */ + + LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R, /* type (122). */ + 0, /* rightshift. */ + 0, /* size. */ + 0, /* bitsize. */ + false, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_TLS_LE_ADD_R", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_TLS_LE_ADD_R, /* bfd_reloc_code_real_type. */ + NULL, /* adjust_reloc_bits. */ + "le_add_r"), /* larch_reloc_type_name. */ + + LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R, /* type (123). */ + 0, /* rightshift. */ + 4, /* size. */ + 12, /* bitsize. */ + false, /* pc_relative. */ + 10, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_TLS_LE_LO12_R", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x3ffc00, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_TLS_LE_LO12_R, /* bfd_reloc_code_real_type. */ + reloc_bits, /* adjust_reloc_bits. */ + "le_lo12_r"), /* larch_reloc_type_name. */ /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. */ LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ @@ -1870,9 +1917,7 @@ reloc_howto_type * loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, bfd_reloc_code_real_type code) { - /* BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); - */ /* Fast search for new reloc types. */ if (BFD_RELOC_LARCH_B16 <= code && code < BFD_RELOC_LARCH_RELAX) diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 196e7e55ea6..a52fabdf7c9 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -3615,6 +3615,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_LARCH_TLS_DESC64_HI12", "BFD_RELOC_LARCH_TLS_DESC_LD", "BFD_RELOC_LARCH_TLS_DESC_CALL", + "BFD_RELOC_LARCH_TLS_LE_HI20_R", + "BFD_RELOC_LARCH_TLS_LE_ADD_R", + "BFD_RELOC_LARCH_TLS_LE_LO12_R", "BFD_RELOC_LARCH_TLS_LD_PCREL20_S2", "BFD_RELOC_LARCH_TLS_GD_PCREL20_S2", "BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2", diff --git a/bfd/reloc.c b/bfd/reloc.c index 30852b1422f..3edcbab51e9 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -8330,6 +8330,13 @@ ENUMX ENUMX BFD_RELOC_LARCH_TLS_DESC_CALL +ENUMX + BFD_RELOC_LARCH_TLS_LE_HI20_R +ENUMX + BFD_RELOC_LARCH_TLS_LE_ADD_R +ENUMX + BFD_RELOC_LARCH_TLS_LE_LO12_R + ENUMX BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 ENUMX