RISC-V: Add pause hint instruction.

Add support for the pause hint instruction, as specified in the
Zihintpause extension.  The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set).  The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Added
    INSN_CLASS_ZIHINTPAUSE.
    * testsuite/gas/riscv/pause.d: New testcase.  Adding coverage for
    the pause hint instruction.
    * testsuite/gas/riscv/pause.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
    for pause hint instruction.
    * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add pause hint instruction.

include/opcode/riscv.h

@@ -311,6 +311,7 @@ enum riscv_insn_class
    INSN_CLASS_D_AND_C,
    INSN_CLASS_ZICSR,
    INSN_CLASS_ZIFENCEI,
+   INSN_CLASS_ZIHINTPAUSE,
    INSN_CLASS_ZBA,
    INSN_CLASS_ZBB,
    INSN_CLASS_ZBC,