Toolchain/binutils-gdb
1
0
Fork 0
forked from Imagelibrary/binutils-gdb
Code Pull Requests Activity

x86: fold Disp32S and Disp32

Browse Source 
The only case where 64-bit code uses non-sign-extended (can also be
considered zero-extended) displacements is when an address size override
is in place for a memory operand (i.e. particularly excluding
displacements of direct branches, which - if at all - are controlled by
operand size, and then are still sign-extended, just from 16 bits).
Hence the distinction in templates is unnecessary, allowing code to be
simplified in a number of places. The only place where logic becomes
more complicated is when signed-ness of relocations is determined in
output_disp().

The other caveat is that Disp64 cannot be specified anymore in an insn
template at the same time as Disp32. Unlike for non-64-bit mode,
templates don't specify displacements for both possible addressing
modes; the necessary adjustment to the expected ones has already been
done in match_template() anyway (but of course the logic there needs
tweaking now). Hence the single template so far doing so is split.
This commit is contained in:
Jan Beulich
2022-07-04 08:32:50 +02:00
parent 02b83698ef
commit a775efc84d
7 changed files with 12928 additions and 12958 deletions
Download Patch File Download Diff File Expand all files Collapse all files

142
opcodes/i386-init.h
View File

@@ -1794,192 +1794,188 @@
#define OPERAND_TYPE_NONE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG8 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG16 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG32 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG64 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM1 \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8 \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8S \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16 \
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32 \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32S \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_BASEINDEX \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SHIFTCOUNT \
{ { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_CONTROL \
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_TEST \
{ { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DEBUG \
{ { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATREG \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0 } }
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATACC \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 0, 0, 0, 0, 0, 0 } }
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SREG \
{ { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGMMX \
{ { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGXMM \
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 1, 0, 0, 0, 0, 0 } }
1, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGYMM \
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0 } }
0, 1, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGZMM \
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0 } }
0, 0, 1, 0, 0, 0 } }
#define OPERAND_TYPE_REGTMM \
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0 } }
0, 0, 0, 1, 0, 0 } }
#define OPERAND_TYPE_REGMASK \
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGBND \
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC8 \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC16 \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC32 \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC64 \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ANYDISP \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32 \
{ { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32S \
{ { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32_32S \
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_64 \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32S_64 \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ANYIMM \
{ { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 } }
0, 0, 0, 0, 0, 0 } }