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PR24390, Don't decode mtfsb field as a cr field

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"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.

	PR 24390
include/
	* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
	* testsuite/gas/ppc/476.d: Update mtfsb*.
	* testsuite/gas/ppc/a2.d: Likewise.
This commit is contained in:
Alan Modra
2019-03-28 10:36:55 +10:30
parent 0720291713
commit 96a86c01d1
8 changed files with 43 additions and 15 deletions
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5
include/opcode/ppc.h
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@@ -354,7 +354,10 @@ extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_CR_BIT (0x20)
/* This is a CR FIELD that does not use symbolic names (unless
-mregnames is in effect). */
-mregnames is in effect). If both PPC_OPERAND_CR_BIT and
PPC_OPERAND_CR_REG are set then treat the field as per
PPC_OPERAND_CR_BIT for assembly, but as if neither of these
bits are set for disassembly. */
#define PPC_OPERAND_CR_REG (0x40)
/* This operand names a special purpose register. */