forked from Imagelibrary/binutils-gdb
* config/i386/tm-i386.h (FP7_REGNUM, FIRST_FPU_CTRL_REGNUM,
FCTRL_REGNUM, FPC_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM, FOP_REGNUM, LAST_FPU_CTRL_REGNUM, XMM0_REGNUM, XMM7_REGNUM, MXCSR_REGNUM, IS_FP_REGNUM, IS_SSE_REGNUM): Removed. (FP0_REGNUM): Define conditionally depending on HAVE_I387_REGS. (SIZEOF_FPU_CTRL_REGS): Hardcode value. * i386-tdep.h (struct gdbarch_tdep): Change such that it contains a single member `num_xmm_regs'. (FPC_REGNUM): New macro. (FIRST_FPU_REGNUM, LAST_FPU_REGNUM, FISRT_XMM_REGNUM, LAST_XMM_REGNUM, MXCSR_REGNUM, FIRST_FPU_CTRL_REGNUM, LAST_FPU_CTRL_REGNUM): Removed. (FCTRL_REGNUM, FSTAT_REGNUM, FTAG_REGNUM, FOP_REGNUM, XMM0_REGNUM, MXCSR_REGNUM): Define unconditionally. Change macros to match the comment describing the register layout. (FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM): New macros. (FP_REGNUM_P, FPC_REGNUM_P, SSE_REGNUM_P): New macros. (IS_FP_REGNUM, IS_FPU_CTRL_REGNUM, IS_SSE_REGNUM): Make obsolete, unconditionally define in terms of FP_REGNUM_P, FPC_REGNUM_P and SSE_REGNUM_P). (FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM): Make obsolete, unconditionally define in terms of FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM, FOOFF_REGNUM. * i386-tdep.c (i386_gdbarch_init): Initialize `num_xmm_regs' member of `struct gdbarch_tdep'. * x86-64-tdep.c (i386_gdbarch_init): Change initialization of `struct gdbarch_tdep'. * i387-nat.c (FCS_REGNUM, FCOFF_REGNUM, FDS_REGNUM, FDOFF_REGNUM): Replace with FISEG_REGNUM, FIOFF_REGNUM, FOSEG_REGNUM and FOOFF_REGNUM. Use FPC_REGNUM instead of FIRST_FPU_CTRL_REGNUM. Use XMM0_REGNUM instead of LAST_FPU_CTRL_REGNUM.
This commit is contained in:
Mark Kettenis
158
gdb/i386-tdep.h
158
gdb/i386-tdep.h
@@ -22,90 +22,92 @@
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#ifndef I386_TDEP_H
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#define I386_TDEP_H
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#define FPU_REG_RAW_SIZE 10
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/* GDB's i386 target supports both the 32-bit Intel Architecture
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(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
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a similar register layout for both.
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#if !defined (XMM0_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define XMM0_REGNUM FIRST_XMM_REGNUM
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#endif
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#if !defined (FIRST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_FPU_REGNUM FP0_REGNUM
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#endif
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#if !defined (LAST_FPU_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_FPU_REGNUM (gdbarch_tdep (current_gdbarch)->last_fpu_regnum)
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#endif
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#if !defined (FIRST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->first_xmm_regnum)
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#endif
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#if !defined (LAST_XMM_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_XMM_REGNUM (gdbarch_tdep (current_gdbarch)->last_xmm_regnum)
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#endif
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#if !defined (MXCSR_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define MXCSR_REGNUM (gdbarch_tdep (current_gdbarch)->mxcsr_regnum)
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#endif
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#if !defined (FIRST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FIRST_FPU_CTRL_REGNUM (gdbarch_tdep (current_gdbarch)->first_fpu_ctrl_regnum)
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#endif
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#if !defined (LAST_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define LAST_FPU_CTRL_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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#endif
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- General purpose registers
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- FPU data registers
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- FPU control registers
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- SSE data registers
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- SSE control register
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/* All of these control registers (except for FCOFF and FDOFF) are
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sixteen bits long (at most) in the FPU, but are zero-extended to
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thirty-two bits in GDB's register file. This makes it easier to
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compute the size of the control register file, and somewhat easier
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to convert to and from the FSAVE instruction's 32-bit format. */
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/* FPU control word. */
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#if !defined (FCTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCTRL_REGNUM (FIRST_FPU_CTRL_REGNUM)
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#endif
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/* FPU status word. */
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#if !defined (FSTAT_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FSTAT_REGNUM (FIRST_FPU_CTRL_REGNUM + 1)
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#endif
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/* FPU register tag word. */
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#if !defined (FTAG_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FTAG_REGNUM (FIRST_FPU_CTRL_REGNUM + 2)
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#endif
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/* FPU instruction's code segment selector 16 bits, called "FPU Instruction
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Pointer Selector" in the x86 manuals. */
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#if !defined (FCS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCS_REGNUM (FIRST_FPU_CTRL_REGNUM + 3)
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#endif
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/* FPU instruction's offset within segment ("Fpu Code OFFset"). */
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#if !defined (FCOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FCOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 4)
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#endif
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/* FPU operand's data segment. */
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#if !defined (FDS_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FDS_REGNUM (FIRST_FPU_CTRL_REGNUM + 5)
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#endif
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/* FPU operand's offset within segment. */
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#if !defined (FDOFF_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FDOFF_REGNUM (FIRST_FPU_CTRL_REGNUM + 6)
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#endif
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/* FPU opcode, bottom eleven bits. */
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#if !defined (FOP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define FOP_REGNUM (FIRST_FPU_CTRL_REGNUM + 7)
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#endif
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The general purpose registers for the x86-64 architecture are quite
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different from IA-32. Therefore, the FP0_REGNUM target macro
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determines the register number at which the FPU data registers
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start. The number of FPU data and control registers is the same
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for both architectures. The number of SSE registers however,
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differs and is determined by the num_xmm_regs member of `struct
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gdbarch_tdep'. */
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/* i386 architecture specific information. */
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struct gdbarch_tdep
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{
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int last_fpu_regnum;
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int first_xmm_regnum;
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int last_xmm_regnum;
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int mxcsr_regnum; /* Streaming SIMD Extension control/status. */
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int first_fpu_ctrl_regnum;
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/* Number of SSE registers. */
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int num_xmm_regs;
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};
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#if !defined (IS_FP_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_FP_REGNUM(n) (FIRST_FPU_REGNUM <= (n) && (n) <= LAST_FPU_REGNUM)
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#endif
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#if !defined (IS_FPU_CTRL_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_FPU_CTRL_REGNUM(n) (FIRST_FPU_CTRL_REGNUM <= (n) && (n) <= LAST_FPU_CTRL_REGNUM)
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#endif
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#if !defined (IS_SSE_REGNUM) || (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
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#define IS_SSE_REGNUM(n) (FIRST_XMM_REGNUM <= (n) && (n) <= LAST_XMM_REGNUM)
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#endif
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/* Floating-point registers. */
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#endif
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#define FPU_REG_RAW_SIZE 10
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/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
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(at most) in the FPU, but are zero-extended to 32 bits in GDB's
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register cache. */
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/* "Generic" floating point control register. */
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#define FPC_REGNUM (FP0_REGNUM + 8)
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/* FPU control word. */
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#define FCTRL_REGNUM FPC_REGNUM
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/* FPU status word. */
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#define FSTAT_REGNUM (FPC_REGNUM + 1)
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/* FPU register tag word. */
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#define FTAG_REGNUM (FPC_REGNUM + 2)
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/* FPU instruction's code segment selector, called "FPU Instruction
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Pointer Selector" in the IA-32 manuals. */
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#define FISEG_REGNUM (FPC_REGNUM + 3)
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/* FPU instruction's offset within segment. */
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#define FIOFF_REGNUM (FPC_REGNUM + 4)
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/* FPU operand's data segment. */
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#define FOSEG_REGNUM (FPC_REGNUM + 5)
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/* FPU operand's offset within segment */
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#define FOOFF_REGNUM (FPC_REGNUM + 6)
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/* FPU opcode, bottom eleven bits. */
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#define FOP_REGNUM (FPC_REGNUM + 7)
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/* Return non-zero if N corresponds to a FPU data registers. */
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#define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM)
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/* Return non-zero if N corresponds to a FPU control register. */
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#define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM)
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/* SSE registers. */
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/* First SSE data register. */
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#define XMM0_REGNUM (FPC_REGNUM + 8)
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/* SSE control/status register. */
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#define MXCSR_REGNUM \
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(XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs)
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/* Return non-zero if N corresponds to a SSE data register. */
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#define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM)
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/* FIXME: kettenis/2001-11-24: Obsolete macro's. */
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#define FCS_REGNUM FISEG_REGNUM
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#define FCOFF_REGNUM FIOFF_REGNUM
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#define FDS_REGNUM FOSEG_REGNUM
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#define FDOFF_REGNUM FOOFF_REGNUM
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#define IS_FP_REGNUM(n) FP_REGNUM_P (n)
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#define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n)
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#define IS_SSE_REGNUM(n) SSE_REGNUM_P (n)
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#endif /* i386-tdep.h */
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