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Add support for instruction level tracing to the ARM simulator.

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* wrapper.c (op_print): New function.
	(sim_dis_read): New function.
	(print_insn): New function - disassembles the given instruction.
	(sim_trace): Note that tracing is now allowed.
	(sim_create_inferior): Default to emulating v6.
	Initialise the disassembler machinery.
	(sim_target_parse_command_line): Add support for -t -d and -z
	options.
	(sim_target_display_usage): Note existence of -d and -z options.
	(sim_open): Parse -t -d and -z options.
	* armemu.h: Add exports of trace, disas and trace_funcs.
	Add prototype for print_insn.
	* armemu.c (ARMul_Emulate26): Add tracing code.
	Delete unused variables.
	* thumbemu (handle_v6_thumb_insn): Delete unused variable Rd.
	Move Rm variable into switch cases.
	Add tracing code.

	* armcopro.c (XScale_cp15_init): Add a return value.
	(XScale_cp13_init): Likewise.
	(XScale_cp14_init): Likewise.
	(XScale_cp15_LDC): Delete unused function.
	(XScale_cp15_STC): Likewise.
	* maverick.c: Delete comment inside comment.
	(DSPInit): Delete unused function.
	(DSPMCR4): Fix compile time warning about missing parenthesis.
	(DSPMCR5): Likewise.
	(DSPCDP6): Delete unused variable opcode2.
This commit is contained in:
Nick Clifton
2014-03-14 15:21:23 +00:00
parent b9366cf395
commit 8d05292667
7 changed files with 245 additions and 94 deletions
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70
sim/arm/thumbemu.c
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@@ -5,12 +5,12 @@
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
@@ -38,9 +38,6 @@ handle_v6_thumb_insn (ARMul_State * state,
ARMword tinstr,
tdstate * pvalid)
{
ARMword Rd;
ARMword Rm;
if (! state->is_v6)
{
* pvalid = t_undefined;
@@ -56,33 +53,48 @@ handle_v6_thumb_insn (ARMul_State * state,
case 0xba40: /* rev16 */
case 0xbac0: /* revsh */
case 0xb650: /* setend */
default:
default:
printf ("Unhandled v6 thumb insn: %04x\n", tinstr);
* pvalid = t_undefined;
return;
case 0xb200: /* sxth */
Rm = state->Reg [(tinstr & 0x38) >> 3];
if (Rm & 0x8000)
state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
else
state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
break;
{
ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
if (Rm & 0x8000)
state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
else
state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
break;
}
case 0xb240: /* sxtb */
Rm = state->Reg [(tinstr & 0x38) >> 3];
if (Rm & 0x80)
state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
else
state->Reg [(tinstr & 0x7)] = Rm & 0xff;
break;
{
ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
if (Rm & 0x80)
state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
else
state->Reg [(tinstr & 0x7)] = Rm & 0xff;
break;
}
case 0xb280: /* uxth */
Rm = state->Reg [(tinstr & 0x38) >> 3];
state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
break;
{
ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
break;
}
case 0xb2c0: /* uxtb */
Rm = state->Reg [(tinstr & 0x38) >> 3];
state->Reg [(tinstr & 0x7)] = Rm & 0xff;
break;
{
ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
state->Reg [(tinstr & 0x7)] = Rm & 0xff;
break;
}
}
/* Indicate that the instruction has been processed. */
* pvalid = t_branch;
@@ -113,6 +125,9 @@ ARMul_ThumbDecode (ARMul_State * state,
tinstr &= 0xFFFF;
}
if (trace)
fprintf (stderr, "pc: %x, Thumb instr: %x", pc & ~1, tinstr);
#if 1 /* debugging to catch non updates */
*ainstr = 0xDEADC0DE;
#endif
@@ -413,7 +428,7 @@ ARMul_ThumbDecode (ARMul_State * state,
case 0x0e00:
if (state->is_v5)
{
/* This is normally an undefined instruction. The v5t architecture
/* This is normally an undefined instruction. The v5t architecture
defines this particular pattern as a BKPT instruction, for
hardware assisted debugging. We map onto the arm BKPT
instruction. */
@@ -550,6 +565,8 @@ ARMul_ThumbDecode (ARMul_State * state,
state->Reg[14] = (tmp | 1);
valid = t_branch;
FLUSHPIPE;
if (trace_funcs)
fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
break;
}
}
@@ -610,5 +627,8 @@ ARMul_ThumbDecode (ARMul_State * state,
break;
}
if (trace && valid != t_decoded)
fprintf (stderr, "\n");
return valid;
}