forked from Imagelibrary/binutils-gdb
New ARC implementation.
bfd * archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
gas * config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
* emulparams/arcebelf_prof.sh: New file
* emulparams/arcebelf.sh: Likewise.
* emulparams/arceblinux_prof.sh: Likewise.
* emulparams/arceblinux.sh: Likewise.
* emulparams/arcelf_prof.sh: Likewise.
* emulparams/arcelf.sh: Likewise.
* emulparams/arclinux_prof.sh: Likewise.
* emulparams/arclinux.sh: Likewise.
* emulparams/arcv2elfx.sh: Likewise.
* emulparams/arcv2elf.sh: Likewise.
* emultempl/arclinux.em: Likewise.
* scripttempl/arclinux.sc: Likewise.
* scripttempl/elfarc.sc: Likewise.
* scripttempl/elfarcv2.sc: Likewise
* Makefile.am: Add new ARC emulations.
* Makefile.in: Regenerate.
* NEWS: Mention the new feature.
opcodes * arc-dis.c: Revamped file for ARC support
* arc-dis.h: Likewise.
* arc-ext.c: Likewise.
* arc-ext.h: Likewise.
* arc-opc.c: Likewise.
* arc-fxi.h: New file.
* arc-regs.h: Likewise.
* arc-tbl.h: Likewise.
binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
include * dis-asm.h (arc_get_disassembler): Correct declaration.
* arc-reloc.def: Macro file with definition of all relocation
types.
* arc.h: Changed macros for the newly supported ARC cpus. Altered
enum defining the supported relocations.
* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
macro for EM_ARC_COMPACT2.
* arc-func.h: New file.
* arc.h: Likewise.
This commit is contained in:
Nick Clifton
@@ -1,3 +1,14 @@
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||||
2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c: Revamped file for ARC support
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* arc-dis.h: Likewise.
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* arc-ext.c: Likewise.
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* arc-ext.h: Likewise.
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* arc-opc.c: Likewise.
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* arc-fxi.h: New file.
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* arc-regs.h: Likewise.
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* arc-tbl.h: Likewise.
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2015-10-02 Yao Qi <yao.qi@linaro.org>
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* aarch64-dis.c (disas_aarch64_insn): Remove static. Change
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1643
opcodes/arc-dis.c
1643
opcodes/arc-dis.c
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,7 @@
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/* Disassembler structures definitions for the ARC.
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Copyright (C) 1994-2015 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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@@ -21,11 +22,15 @@
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#ifndef ARCDIS_H
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#define ARCDIS_H
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enum
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enum ARC_Debugger_OperandType
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{
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BR_exec_when_no_jump,
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BR_exec_always,
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BR_exec_when_jump
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ARC_UNDEFINED,
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ARC_LIMM,
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ARC_SHIMM,
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ARC_REGISTER,
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ARCOMPACT_REGISTER /* Valid only for the
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registers allowed in
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16 bit mode. */
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};
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enum Flow
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@@ -38,7 +43,13 @@ enum Flow
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invalid_instr
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};
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enum { no_reg = 99 };
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enum NullifyMode
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{
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BR_exec_when_no_jump,
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BR_exec_always,
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BR_exec_when_jump
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};
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enum { allOperandsSize = 256 };
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struct arcDisState
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@@ -53,10 +64,21 @@ struct arcDisState
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unsigned char* instruction;
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unsigned index;
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const char *comm[6]; /* instr name, cond, NOP, 3 operands */
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const char *comm[6]; /* Instr name, cond, NOP, 3 operands. */
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union
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{
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unsigned int registerNum;
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unsigned int shortimm;
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unsigned int longimm;
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} source_operand;
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enum ARC_Debugger_OperandType sourceType;
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int opWidth;
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int targets[4];
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int addresses[4];
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/* START ARC LOCAL. */
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unsigned int addresses[4];
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/* END ARC LOCAL. */
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/* Set as a side-effect of calling the disassembler.
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Used only by the debugger. */
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enum Flow flow;
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@@ -68,15 +90,16 @@ struct arcDisState
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char instrBuffer[40];
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char operandBuffer[allOperandsSize];
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char _ea_present;
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char _addrWriteBack; /* Address writeback. */
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char _mem_load;
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char _load_len;
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char nullifyMode;
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enum NullifyMode nullifyMode;
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unsigned char commNum;
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unsigned char isBranch;
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unsigned char tcnt;
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unsigned char acnt;
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};
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#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
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struct arcDisState
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arcAnalyzeInstr (bfd_vma memaddr, struct disassemble_info *);
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#endif
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@@ -1,4 +1,4 @@
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/* ARC target-dependent stuff. Extension structure access functions
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/* ARC target-dependent stuff. Extension structure access functions
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Copyright (C) 1995-2015 Free Software Foundation, Inc.
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This file is part of libopcodes.
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@@ -21,137 +21,88 @@
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#include "sysdep.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include "bfd.h"
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#include "arc-ext.h"
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#include "elf/arc.h"
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#include "libiberty.h"
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/* Extension structure */
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/* This module provides support for extensions to the ARC processor
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architecture. */
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/* Local constants. */
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#define FIRST_EXTENSION_CORE_REGISTER 32
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#define LAST_EXTENSION_CORE_REGISTER 59
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#define FIRST_EXTENSION_CONDITION_CODE 0x10
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#define LAST_EXTENSION_CONDITION_CODE 0x1f
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#define NUM_EXT_CORE \
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(LAST_EXTENSION_CORE_REGISTER - FIRST_EXTENSION_CORE_REGISTER + 1)
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#define NUM_EXT_COND \
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(LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1)
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#define INST_HASH_BITS 6
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#define INST_HASH_SIZE (1 << INST_HASH_BITS)
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#define INST_HASH_MASK (INST_HASH_SIZE - 1)
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/* Local types. */
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/* These types define the information stored in the table. */
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struct ExtInstruction
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{
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char major;
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char minor;
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char flags;
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char* name;
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struct ExtInstruction* next;
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};
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struct ExtAuxRegister
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{
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long address;
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char* name;
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struct ExtAuxRegister* next;
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};
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struct ExtCoreRegister
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{
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short number;
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enum ExtReadWrite rw;
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char* name;
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};
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struct arcExtMap
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{
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struct ExtAuxRegister* auxRegisters;
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struct ExtInstruction* instructions[INST_HASH_SIZE];
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struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
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char* condCodes[NUM_EXT_COND];
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};
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/* Local data. */
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/* Extension table. */
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static struct arcExtMap arc_extension_map;
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/* Get the name of an extension instruction. */
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const char *
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arcExtMap_instName(int opcode, int minor, int *flags)
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{
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if (opcode == 3)
|
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{
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/* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */
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if (minor < 0x09 || minor == 0x3f)
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return 0;
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else
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opcode = 0x1f - 0x10 + minor - 0x09 + 1;
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}
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else
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if (opcode < 0x10)
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return 0;
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else
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opcode -= 0x10;
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if (!arc_extension_map.instructions[opcode])
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return 0;
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*flags = arc_extension_map.instructions[opcode]->flags;
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return arc_extension_map.instructions[opcode]->name;
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}
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/* Local macros. */
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/* Get the name of an extension core register. */
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/* A hash function used to map instructions into the table. */
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#define INST_HASH(MAJOR, MINOR) ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK)
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const char *
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arcExtMap_coreRegName(int value)
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{
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if (value < 32)
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return 0;
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return arc_extension_map.coreRegisters[value-32];
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}
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/* Get the name of an extension condition code. */
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const char *
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arcExtMap_condCodeName(int value)
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{
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if (value < 16)
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return 0;
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return arc_extension_map.condCodes[value-16];
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}
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/* Get the name of an extension aux register. */
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const char *
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arcExtMap_auxRegName(long address)
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{
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/* walk the list of aux reg names and find the name */
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struct ExtAuxRegister *r;
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for (r = arc_extension_map.auxRegisters; r; r = r->next) {
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if (r->address == address)
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return (const char *) r->name;
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}
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return 0;
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}
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||||
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||||
/* Recursively free auxilliary register strcture pointers until
|
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the list is empty. */
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/* Local functions. */
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||||
static void
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clean_aux_registers(struct ExtAuxRegister *r)
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create_map (unsigned char *block,
|
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unsigned long length)
|
||||
{
|
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if (r -> next)
|
||||
{
|
||||
clean_aux_registers( r->next);
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||||
free(r -> name);
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free(r -> next);
|
||||
r ->next = NULL;
|
||||
}
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||||
else
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||||
free(r -> name);
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||||
}
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||||
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||||
/* Free memory that has been allocated for the extensions. */
|
||||
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||||
static void
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||||
cleanup_ext_map(void)
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{
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||||
struct ExtAuxRegister *r;
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struct ExtInstruction *insn;
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int i;
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/* clean aux reg structure */
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r = arc_extension_map.auxRegisters;
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if (r)
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{
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(clean_aux_registers(r));
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free(r);
|
||||
}
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||||
|
||||
/* clean instructions */
|
||||
for (i = 0; i < NUM_EXT_INST; i++)
|
||||
{
|
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insn = arc_extension_map.instructions[i];
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||||
if (insn)
|
||||
free(insn->name);
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||||
}
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|
||||
/* clean core reg struct */
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for (i = 0; i < NUM_EXT_CORE; i++)
|
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{
|
||||
if (arc_extension_map.coreRegisters[i])
|
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free(arc_extension_map.coreRegisters[i]);
|
||||
}
|
||||
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||||
for (i = 0; i < NUM_EXT_COND; i++) {
|
||||
if (arc_extension_map.condCodes[i])
|
||||
free(arc_extension_map.condCodes[i]);
|
||||
}
|
||||
|
||||
memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
|
||||
}
|
||||
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||||
int
|
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arcExtMap_add(void *base, unsigned long length)
|
||||
{
|
||||
unsigned char *block = (unsigned char *) base;
|
||||
unsigned char *p = (unsigned char *) block;
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||||
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||||
/* Clean up and reset everything if needed. */
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||||
cleanup_ext_map();
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||||
unsigned char *p = block;
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||||
|
||||
while (p && p < (block + length))
|
||||
{
|
||||
@@ -165,97 +116,384 @@ arcExtMap_add(void *base, unsigned long length)
|
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For core regs and condition codes:
|
||||
p[2] = value
|
||||
p[3]+ = name
|
||||
For aux regs:
|
||||
For auxiliary regs:
|
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p[2..5] = value
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p[6]+ = name
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||||
(value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */
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(value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]). */
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||||
|
||||
/* The sequence of records is temrinated by an "empty"
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||||
record. */
|
||||
if (p[0] == 0)
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||||
return -1;
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||||
break;
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||||
|
||||
switch (p[1])
|
||||
{
|
||||
case EXT_INSTRUCTION:
|
||||
{
|
||||
char opcode = p[2];
|
||||
char minor = p[3];
|
||||
char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
|
||||
struct ExtInstruction * insn =
|
||||
(struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
|
||||
struct ExtInstruction *insn = XNEW (struct ExtInstruction);
|
||||
int major = p[2];
|
||||
int minor = p[3];
|
||||
struct ExtInstruction **bucket =
|
||||
&arc_extension_map.instructions[INST_HASH (major, minor)];
|
||||
|
||||
if (opcode==3)
|
||||
opcode = 0x1f - 0x10 + minor - 0x09 + 1;
|
||||
else
|
||||
opcode -= 0x10;
|
||||
insn -> flags = (char) *(p+4);
|
||||
strcpy (insn_name, (char *) (p+5));
|
||||
insn -> name = insn_name;
|
||||
arc_extension_map.instructions[(int) opcode] = insn;
|
||||
insn->name = xstrdup ((char *) (p + 5));
|
||||
insn->major = major;
|
||||
insn->minor = minor;
|
||||
insn->flags = p[4];
|
||||
insn->next = *bucket;
|
||||
*bucket = insn;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case EXT_CORE_REGISTER:
|
||||
{
|
||||
char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
|
||||
unsigned char number = p[2];
|
||||
char* name = (char *) (p + 3);
|
||||
|
||||
strcpy(core_name, (char *) (p+3));
|
||||
arc_extension_map.coreRegisters[p[2]-32] = core_name;
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
|
||||
= number;
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
|
||||
= REG_READWRITE;
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
|
||||
= xstrdup (name);
|
||||
break;
|
||||
}
|
||||
|
||||
case EXT_LONG_CORE_REGISTER:
|
||||
{
|
||||
unsigned char number = p[2];
|
||||
char* name = (char *) (p + 7);
|
||||
enum ExtReadWrite rw = p[6];
|
||||
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
|
||||
= number;
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
|
||||
= rw;
|
||||
arc_extension_map.
|
||||
coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
|
||||
= xstrdup (name);
|
||||
}
|
||||
break;
|
||||
|
||||
case EXT_COND_CODE:
|
||||
{
|
||||
char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
|
||||
strcpy(cc_name, (char *) (p+3));
|
||||
arc_extension_map.condCodes[p[2]-16] = cc_name;
|
||||
char *cc_name = xstrdup ((char *) (p + 3));
|
||||
|
||||
arc_extension_map.
|
||||
condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE]
|
||||
= cc_name;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case EXT_AUX_REGISTER:
|
||||
{
|
||||
/* trickier -- need to store linked list to these */
|
||||
struct ExtAuxRegister *newAuxRegister =
|
||||
(struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
|
||||
char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
|
||||
/* Trickier -- need to store linked list of these. */
|
||||
struct ExtAuxRegister *newAuxRegister
|
||||
= XNEW (struct ExtAuxRegister);
|
||||
char *aux_name = xstrdup ((char *) (p + 6));
|
||||
|
||||
strcpy (aux_name, (char *) (p+6));
|
||||
newAuxRegister->name = aux_name;
|
||||
newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5];
|
||||
newAuxRegister->address = (p[2] << 24) | (p[3] << 16)
|
||||
| (p[4] << 8) | p[5];
|
||||
newAuxRegister->next = arc_extension_map.auxRegisters;
|
||||
arc_extension_map.auxRegisters = newAuxRegister;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return -1;
|
||||
|
||||
break;
|
||||
}
|
||||
p += p[0]; /* move to next record */
|
||||
|
||||
p += p[0]; /* Move on to next record. */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Free memory that has been allocated for the extensions. */
|
||||
|
||||
static void
|
||||
destroy_map (void)
|
||||
{
|
||||
struct ExtAuxRegister *r;
|
||||
unsigned int i;
|
||||
|
||||
/* Free auxiliary registers. */
|
||||
r = arc_extension_map.auxRegisters;
|
||||
while (r)
|
||||
{
|
||||
/* N.B. after r has been freed, r->next is invalid! */
|
||||
struct ExtAuxRegister* next = r->next;
|
||||
|
||||
free (r->name);
|
||||
free (r);
|
||||
r = next;
|
||||
}
|
||||
|
||||
return 0;
|
||||
/* Free instructions. */
|
||||
for (i = 0; i < INST_HASH_SIZE; i++)
|
||||
{
|
||||
struct ExtInstruction *insn = arc_extension_map.instructions[i];
|
||||
|
||||
while (insn)
|
||||
{
|
||||
/* N.B. after insn has been freed, insn->next is invalid! */
|
||||
struct ExtInstruction *next = insn->next;
|
||||
|
||||
free (insn->name);
|
||||
free (insn);
|
||||
insn = next;
|
||||
}
|
||||
}
|
||||
|
||||
/* Free core registers. */
|
||||
for (i = 0; i < NUM_EXT_CORE; i++)
|
||||
{
|
||||
if (arc_extension_map.coreRegisters[i].name)
|
||||
free (arc_extension_map.coreRegisters[i].name);
|
||||
}
|
||||
|
||||
/* Free condition codes. */
|
||||
for (i = 0; i < NUM_EXT_COND; i++)
|
||||
{
|
||||
if (arc_extension_map.condCodes[i])
|
||||
free (arc_extension_map.condCodes[i]);
|
||||
}
|
||||
|
||||
memset (&arc_extension_map, 0, sizeof (arc_extension_map));
|
||||
}
|
||||
|
||||
/* Load hw extension descibed in .extArcMap ELF section. */
|
||||
|
||||
static const char *
|
||||
ExtReadWrite_image (enum ExtReadWrite val)
|
||||
{
|
||||
switch (val)
|
||||
{
|
||||
case REG_INVALID : return "INVALID";
|
||||
case REG_READ : return "RO";
|
||||
case REG_WRITE : return "WO";
|
||||
case REG_READWRITE: return "R/W";
|
||||
default : return "???";
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Externally visible functions. */
|
||||
|
||||
/* Get the name of an extension instruction. */
|
||||
|
||||
const char *
|
||||
arcExtMap_instName (int opcode,
|
||||
int insn,
|
||||
int *flags)
|
||||
{
|
||||
/* Here the following tasks need to be done. First of all, the
|
||||
opcode stored in the Extension Map is the real opcode. However,
|
||||
the subopcode stored in the instruction to be disassembled is
|
||||
mangled. We pass (in minor opcode), the instruction word. Here
|
||||
we will un-mangle it and get the real subopcode which we can look
|
||||
for in the Extension Map. This function is used both for the
|
||||
ARCTangent and the ARCompact, so we would also need some sort of
|
||||
a way to distinguish between the two architectures. This is
|
||||
because the ARCTangent does not do any of this mangling so we
|
||||
have no issues there. */
|
||||
|
||||
/* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1
|
||||
then use iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0
|
||||
then un-mangle using iiiiiI else iiiiii. */
|
||||
|
||||
unsigned char minor;
|
||||
struct ExtInstruction *temp;
|
||||
|
||||
/* 16-bit instructions. */
|
||||
if (0x08 <= opcode && opcode <= 0x0b)
|
||||
{
|
||||
unsigned char b, c, i;
|
||||
|
||||
b = (insn & 0x0700) >> 8;
|
||||
c = (insn & 0x00e0) >> 5;
|
||||
i = (insn & 0x001f);
|
||||
|
||||
if (i)
|
||||
minor = i;
|
||||
else
|
||||
minor = (c == 0x07) ? b : c;
|
||||
}
|
||||
/* 32-bit instructions. */
|
||||
else
|
||||
{
|
||||
unsigned char I, A, B;
|
||||
|
||||
I = (insn & 0x003f0000) >> 16;
|
||||
A = (insn & 0x0000003f);
|
||||
B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
|
||||
|
||||
if (I != 0x2f)
|
||||
{
|
||||
#ifndef UNMANGLED
|
||||
switch (P)
|
||||
{
|
||||
case 3:
|
||||
if (M)
|
||||
{
|
||||
minor = I;
|
||||
break;
|
||||
}
|
||||
case 0:
|
||||
case 2:
|
||||
minor = (I >> 1) | ((I & 0x1) << 5);
|
||||
break;
|
||||
case 1:
|
||||
minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
|
||||
}
|
||||
#else
|
||||
minor = I;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
if (A != 0x3f)
|
||||
minor = A;
|
||||
else
|
||||
minor = B;
|
||||
}
|
||||
}
|
||||
|
||||
temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
|
||||
while (temp)
|
||||
{
|
||||
if ((temp->major == opcode) && (temp->minor == minor))
|
||||
{
|
||||
*flags = temp->flags;
|
||||
return temp->name;
|
||||
}
|
||||
temp = temp->next;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Get the name of an extension core register. */
|
||||
|
||||
const char *
|
||||
arcExtMap_coreRegName (int regnum)
|
||||
{
|
||||
if (regnum < FIRST_EXTENSION_CORE_REGISTER
|
||||
|| regnum > LAST_EXTENSION_CONDITION_CODE)
|
||||
return NULL;
|
||||
return arc_extension_map.
|
||||
coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
|
||||
}
|
||||
|
||||
/* Get the access mode of an extension core register. */
|
||||
|
||||
enum ExtReadWrite
|
||||
arcExtMap_coreReadWrite (int regnum)
|
||||
{
|
||||
if (regnum < FIRST_EXTENSION_CORE_REGISTER
|
||||
|| regnum > LAST_EXTENSION_CONDITION_CODE)
|
||||
return REG_INVALID;
|
||||
return arc_extension_map.
|
||||
coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
|
||||
}
|
||||
|
||||
/* Get the name of an extension condition code. */
|
||||
|
||||
const char *
|
||||
arcExtMap_condCodeName (int code)
|
||||
{
|
||||
if (code < FIRST_EXTENSION_CONDITION_CODE
|
||||
|| code > LAST_EXTENSION_CONDITION_CODE)
|
||||
return NULL;
|
||||
return arc_extension_map.
|
||||
condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
|
||||
}
|
||||
|
||||
/* Get the name of an extension auxiliary register. */
|
||||
|
||||
const char *
|
||||
arcExtMap_auxRegName (long address)
|
||||
{
|
||||
/* Walk the list of auxiliary register names and find the name. */
|
||||
struct ExtAuxRegister *r;
|
||||
|
||||
for (r = arc_extension_map.auxRegisters; r; r = r->next)
|
||||
{
|
||||
if (r->address == address)
|
||||
return (const char *)r->name;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Load extensions described in .arcextmap and
|
||||
.gnu.linkonce.arcextmap.* ELF section. */
|
||||
|
||||
void
|
||||
build_ARC_extmap (text_bfd)
|
||||
bfd *text_bfd;
|
||||
build_ARC_extmap (bfd *text_bfd)
|
||||
{
|
||||
char *arcExtMap;
|
||||
bfd_size_type count;
|
||||
asection *p;
|
||||
asection *sect;
|
||||
|
||||
for (p = text_bfd->sections; p != NULL; p = p->next)
|
||||
if (!strcmp (p->name, ".arcextmap"))
|
||||
/* The map is built each time gdb loads an executable file - so free
|
||||
any existing map, as the map defined by the new file may differ
|
||||
from the old. */
|
||||
destroy_map ();
|
||||
|
||||
for (sect = text_bfd->sections; sect != NULL; sect = sect->next)
|
||||
if (!strncmp (sect->name,
|
||||
".gnu.linkonce.arcextmap.",
|
||||
sizeof (".gnu.linkonce.arcextmap.") - 1)
|
||||
|| !strcmp (sect->name,".arcextmap"))
|
||||
{
|
||||
count = bfd_get_section_size (p);
|
||||
arcExtMap = (char *) xmalloc (count);
|
||||
if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
|
||||
{
|
||||
arcExtMap_add ((PTR) arcExtMap, count);
|
||||
break;
|
||||
}
|
||||
free ((PTR) arcExtMap);
|
||||
bfd_size_type count = bfd_get_section_size (sect);
|
||||
unsigned char* buffer = xmalloc (count);
|
||||
|
||||
if (buffer)
|
||||
{
|
||||
if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count))
|
||||
create_map (buffer, count);
|
||||
free (buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
dump_ARC_extmap (void)
|
||||
{
|
||||
struct ExtAuxRegister *r;
|
||||
int i;
|
||||
|
||||
r = arc_extension_map.auxRegisters;
|
||||
|
||||
while (r)
|
||||
{
|
||||
printf ("AUX : %s %ld\n", r->name, r->address);
|
||||
r = r->next;
|
||||
}
|
||||
|
||||
for (i = 0; i < INST_HASH_SIZE; i++)
|
||||
{
|
||||
struct ExtInstruction *insn;
|
||||
|
||||
for (insn = arc_extension_map.instructions[i];
|
||||
insn != NULL; insn = insn->next)
|
||||
printf ("INST: %d %d %x %s\n", insn->major, insn->minor,
|
||||
insn->flags, insn->name);
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_EXT_CORE; i++)
|
||||
{
|
||||
struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
|
||||
|
||||
if (reg.name)
|
||||
printf ("CORE: %s %d %s\n", reg.name, reg.number,
|
||||
ExtReadWrite_image (reg.rw));
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_EXT_COND; i++)
|
||||
if (arc_extension_map.condCodes[i])
|
||||
printf ("COND: %s\n", arc_extension_map.condCodes[i]);
|
||||
}
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/* ARC target-dependent stuff. Extension data structures.
|
||||
/* ARC target-dependent stuff. Extension data structures.
|
||||
Copyright (C) 1995-2015 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of libopcodes.
|
||||
@@ -18,46 +18,72 @@
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#ifndef ARCEXT_H
|
||||
#define ARCEXT_H
|
||||
/*This header file defines a table of extensions to the ARC processor
|
||||
architecture. These extensions are read from the '.arcextmap' or
|
||||
'.gnu.linkonce.arcextmap.<type>.<N>' sections in the ELF file which
|
||||
is identified by the bfd parameter to the build_ARC_extmap function.
|
||||
|
||||
enum {EXT_INSTRUCTION = 0,
|
||||
EXT_CORE_REGISTER = 1,
|
||||
EXT_AUX_REGISTER = 2,
|
||||
EXT_COND_CODE = 3};
|
||||
These extensions may include:
|
||||
core registers
|
||||
auxiliary registers
|
||||
instructions
|
||||
condition codes
|
||||
|
||||
enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
|
||||
enum {NUM_EXT_CORE = 59-32+1};
|
||||
enum {NUM_EXT_COND = 0x1f-0x10+1};
|
||||
Once the table has been constructed, accessor functions may be used
|
||||
to retrieve information from it.
|
||||
|
||||
struct ExtInstruction
|
||||
{
|
||||
char flags;
|
||||
char *name;
|
||||
};
|
||||
The build_ARC_extmap constructor function build_ARC_extmap may be
|
||||
called as many times as required; it will re-initialize the table
|
||||
each time. */
|
||||
|
||||
struct ExtAuxRegister
|
||||
{
|
||||
long address;
|
||||
char *name;
|
||||
struct ExtAuxRegister *next;
|
||||
};
|
||||
|
||||
struct arcExtMap
|
||||
{
|
||||
struct ExtAuxRegister *auxRegisters;
|
||||
struct ExtInstruction *instructions[NUM_EXT_INST];
|
||||
char *coreRegisters[NUM_EXT_CORE];
|
||||
char *condCodes[NUM_EXT_COND];
|
||||
};
|
||||
|
||||
extern int arcExtMap_add(void*, unsigned long);
|
||||
extern const char *arcExtMap_coreRegName(int);
|
||||
extern const char *arcExtMap_auxRegName(long);
|
||||
extern const char *arcExtMap_condCodeName(int);
|
||||
extern const char *arcExtMap_instName(int, int, int*);
|
||||
extern void build_ARC_extmap(bfd *);
|
||||
#ifndef ARC_EXTENSIONS_H
|
||||
#define ARC_EXTENSIONS_H
|
||||
|
||||
#define IGNORE_FIRST_OPD 1
|
||||
|
||||
#endif
|
||||
/* Define this if we do not want to encode instructions based on the
|
||||
ARCompact Programmer's Reference. */
|
||||
#define UNMANGLED
|
||||
|
||||
|
||||
/* This defines the kinds of extensions which may be read from the
|
||||
ections in the executable files. */
|
||||
enum ExtOperType
|
||||
{
|
||||
EXT_INSTRUCTION = 0,
|
||||
EXT_CORE_REGISTER = 1,
|
||||
EXT_AUX_REGISTER = 2,
|
||||
EXT_COND_CODE = 3,
|
||||
EXT_INSTRUCTION32 = 4,
|
||||
EXT_AC_INSTRUCTION = 4,
|
||||
EXT_REMOVE_CORE_REG = 5,
|
||||
EXT_LONG_CORE_REGISTER = 6,
|
||||
EXT_AUX_REGISTER_EXTENDED = 7,
|
||||
EXT_INSTRUCTION32_EXTENDED = 8,
|
||||
EXT_CORE_REGISTER_CLASS = 9
|
||||
};
|
||||
|
||||
|
||||
enum ExtReadWrite
|
||||
{
|
||||
REG_INVALID,
|
||||
REG_READ,
|
||||
REG_WRITE,
|
||||
REG_READWRITE
|
||||
};
|
||||
|
||||
|
||||
/* Constructor function. */
|
||||
extern void build_ARC_extmap (bfd *);
|
||||
|
||||
/* Accessor functions. */
|
||||
extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
|
||||
extern const char * arcExtMap_coreRegName (int);
|
||||
extern const char * arcExtMap_auxRegName (long);
|
||||
extern const char * arcExtMap_condCodeName (int);
|
||||
extern const char * arcExtMap_instName (int, int, int *);
|
||||
|
||||
/* Dump function (for debugging). */
|
||||
extern void dump_ARC_extmap (void);
|
||||
|
||||
#endif /* ARC_EXTENSIONS_H */
|
||||
|
||||
1317
opcodes/arc-fxi.h
Normal file
1317
opcodes/arc-fxi.h
Normal file
File diff suppressed because it is too large
Load Diff
2897
opcodes/arc-opc.c
2897
opcodes/arc-opc.c
File diff suppressed because it is too large
Load Diff
403
opcodes/arc-regs.h
Normal file
403
opcodes/arc-regs.h
Normal file
@@ -0,0 +1,403 @@
|
||||
/* ARC Auxiliary register definitions
|
||||
Copyright (C) 2015 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
|
||||
|
||||
This file is part of libopcodes.
|
||||
|
||||
This library is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software Foundation,
|
||||
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
DEF (0x0, STATUS)
|
||||
DEF (0x1, SEMAPHORE)
|
||||
DEF (0x2, LP_START)
|
||||
DEF (0x3, LP_END)
|
||||
DEF (0x4, IDENTITY)
|
||||
DEF (0x5, DEBUG)
|
||||
DEF (0x6, PC)
|
||||
DEF (0x7, ADCR)
|
||||
DEF (0x8, APCR)
|
||||
DEF (0x9, ACR)
|
||||
DEF (0xA, STATUS32)
|
||||
DEF (0xB, STATUS32_L1)
|
||||
DEF (0xC, STATUS32_L2)
|
||||
DEF (0xF, BPU_FLUSH)
|
||||
DEF (0x10, IVIC)
|
||||
DEF (0x10, IC_IVIC)
|
||||
DEF (0x11, CHE_MODE)
|
||||
DEF (0x11, IC_CTRL)
|
||||
DEF (0x12, MULHI)
|
||||
DEF (0x13, LOCKLINE)
|
||||
DEF (0x13, IC_LIL)
|
||||
DEF (0x14, DMC_CODE_RAM)
|
||||
DEF (0x15, TAG_ADDR_MASK)
|
||||
DEF (0x16, TAG_DATA_MASK)
|
||||
DEF (0x17, LINE_LENGTH_MASK)
|
||||
DEF (0x18, AUX_LDST_RAM)
|
||||
DEF (0x18, AUX_DCCM)
|
||||
DEF (0x19, UNLOCKLINE)
|
||||
DEF (0x19, IC_IVIL)
|
||||
DEF (0x1A, IC_RAM_ADDRESS)
|
||||
DEF (0x1A, IC_RAM_ADDRESS)
|
||||
DEF (0x1B, IC_TAG)
|
||||
DEF (0x1B, IC_TAG)
|
||||
DEF (0x1C, IC_WP)
|
||||
DEF (0x1C, IC_WP)
|
||||
DEF (0x1D, IC_DATA)
|
||||
DEF (0x1D, IC_DATA)
|
||||
DEF (0x20, SRAM_SEQ)
|
||||
DEF (0x21, COUNT0)
|
||||
DEF (0x22, CONTROL0)
|
||||
DEF (0x22, CONTROL0)
|
||||
DEF (0x23, LIMIT0)
|
||||
DEF (0x24, PCPORT)
|
||||
DEF (0x25, INT_VECTOR_BASE)
|
||||
DEF (0x26, AUX_VBFDW_MODE)
|
||||
DEF (0x26, JLI_BASE)
|
||||
DEF (0x27, AUX_VBFDW_BM0)
|
||||
DEF (0x28, AUX_VBFDW_BM1)
|
||||
DEF (0x29, AUX_VBFDW_ACCU)
|
||||
DEF (0x2A, AUX_VBFDW_OFST)
|
||||
DEF (0x2B, AUX_VBFDW_INTSTAT)
|
||||
DEF (0x2C, AX2 (A4))
|
||||
DEF (0x2C, AUX_XMAC0_24)
|
||||
DEF (0x2D, AY2 (A4))
|
||||
DEF (0x2D, AUX_XMAC1_24)
|
||||
DEF (0x2E, MX2 (A4))
|
||||
DEF (0x2E, AUX_XMAC2_24)
|
||||
DEF (0x2F, MY2 (A4))
|
||||
DEF (0x2F, AUX_FBF_STORE_16)
|
||||
DEF (0x30, AX0)
|
||||
DEF (0x31, AX1)
|
||||
DEF (0x32, AY0 (A4))
|
||||
DEF (0x32, AUX_CRC_POLY)
|
||||
DEF (0x33, AY1 (A4))
|
||||
DEF (0x33, AUX_CRC_MODE)
|
||||
DEF (0x34, MX0)
|
||||
DEF (0x35, MX1)
|
||||
DEF (0x36, MY0)
|
||||
DEF (0x37, MY1)
|
||||
DEF (0x38, XYCONFIG)
|
||||
DEF (0x39, SCRATCH_A)
|
||||
DEF (0x3A, BURSTSYS)
|
||||
DEF (0x3A, TSCH)
|
||||
DEF (0x3B, BURSTXYM)
|
||||
DEF (0x3C, BURSTSZ)
|
||||
DEF (0x3D, BURSTVAL)
|
||||
DEF (0x40, XTP_NEWVAL)
|
||||
DEF (0x41, AUX_MACMODE)
|
||||
DEF (0x42, LSP_NEWVAL)
|
||||
DEF (0x43, AUX_IRQ_LV12)
|
||||
DEF (0x44, AUX_XMAC0)
|
||||
DEF (0x45, AUX_XMAC1)
|
||||
DEF (0x46, AUX_XMAC2)
|
||||
DEF (0x47, DC_IVDC)
|
||||
DEF (0x48, DC_CTRL)
|
||||
DEF (0x49, DC_LDL)
|
||||
DEF (0x4A, DC_IVDL)
|
||||
DEF (0x4B, DC_FLSH)
|
||||
DEF (0x4C, DC_FLDL)
|
||||
DEF (0x50, HEXDATA)
|
||||
DEF (0x51, HEXCTRL)
|
||||
DEF (0x52, LED)
|
||||
DEF (0x53, LCDINSTR (A4))
|
||||
DEF (0x54, LCDDATA (A4))
|
||||
DEF (0x55, LCDSTAT (A4))
|
||||
DEF (0x56, DILSTAT)
|
||||
DEF (0x57, SWSTAT)
|
||||
DEF (0x58, DC_RAM_ADDR)
|
||||
DEF (0x58, DC_RAM_ADDR)
|
||||
DEF (0x59, DC_TAG)
|
||||
DEF (0x59, DC_TAG)
|
||||
DEF (0x5A, DC_WP)
|
||||
DEF (0x5B, DC_DATA)
|
||||
DEF (0x61, DCCM_BASE_BUILD)
|
||||
DEF (0x62, CRC_BUILD)
|
||||
DEF (0x63, BTA_LINK_BUILD)
|
||||
DEF (0x64, VBFDW_BUILD)
|
||||
DEF (0x65, EA_BUILD)
|
||||
DEF (0x66, DATASPACE)
|
||||
DEF (0x67, MEMSUBSYS)
|
||||
DEF (0x68, VECBASE_AC_BUILD)
|
||||
DEF (0x69, P_BASE_ADDR)
|
||||
DEF (0x6A, DATA_UNCACHED_BUILD)
|
||||
DEF (0x6B, FP_BUILD)
|
||||
DEF (0x6C, DPFP_BUILD)
|
||||
DEF (0x6D, MPU_BUILD)
|
||||
DEF (0x6E, RF_BUILD)
|
||||
DEF (0x6F, MMU_BUILD)
|
||||
DEF (0x70, AA2_BUILD)
|
||||
DEF (0x71, VECBASE_BUILD)
|
||||
DEF (0x72, D_CACHE_BUILD)
|
||||
DEF (0x73, MADI_BUILD)
|
||||
DEF (0x74, DCCM_BUILD)
|
||||
DEF (0x75, TIMER_BUILD)
|
||||
DEF (0x76, AP_BUILD)
|
||||
DEF (0x77, I_CACHE_BUILD)
|
||||
DEF (0x78, ICCM_BUILD)
|
||||
DEF (0x79, DSPRAM_BUILD)
|
||||
DEF (0x7A, MAC_BUILD)
|
||||
DEF (0x7B, MULTIPLY_BUILD)
|
||||
DEF (0x7C, SWAP_BUILD)
|
||||
DEF (0x7D, NORM_BUILD)
|
||||
DEF (0x7E, MINMAX_BUILD)
|
||||
DEF (0x7F, BARREL_BUILD)
|
||||
DEF (0x80, AX0)
|
||||
DEF (0x81, AX1)
|
||||
DEF (0x82, AX2)
|
||||
DEF (0x83, AX3)
|
||||
DEF (0x84, AY0)
|
||||
DEF (0x85, AY1)
|
||||
DEF (0x86, AY2)
|
||||
DEF (0x87, AY3)
|
||||
DEF (0x88, MX00)
|
||||
DEF (0x89, MX01)
|
||||
DEF (0x8A, MX10)
|
||||
DEF (0x8B, MX11)
|
||||
DEF (0x8C, MX20)
|
||||
DEF (0x8D, MX21)
|
||||
DEF (0x8E, MX30)
|
||||
DEF (0x8F, MX31)
|
||||
DEF (0x90, MY00)
|
||||
DEF (0x91, MY01)
|
||||
DEF (0x92, MY10)
|
||||
DEF (0x93, MY11)
|
||||
DEF (0x94, MY20)
|
||||
DEF (0x95, MY21)
|
||||
DEF (0x96, MY30)
|
||||
DEF (0x97, MY31)
|
||||
DEF (0x98, XYCONFIG)
|
||||
DEF (0x99, BURSTSYS)
|
||||
DEF (0x9A, BURSTXYM)
|
||||
DEF (0x9B, BURSTSZ)
|
||||
DEF (0x9C, BURSTVAL)
|
||||
DEF (0x9D, XYLSBASEX)
|
||||
DEF (0x9E, XYLSBASEY)
|
||||
DEF (0x9F, AUX_XMACLW_H)
|
||||
DEF (0xA0, AUX_XMACLW_L)
|
||||
DEF (0xA1, SE_CTRL)
|
||||
DEF (0xA2, SE_STAT)
|
||||
DEF (0xA3, SE_ERR)
|
||||
DEF (0xA4, SE_EADR)
|
||||
DEF (0xA5, SE_SPC)
|
||||
DEF (0xA6, SDM_BASE)
|
||||
DEF (0xA7, SCM_BASE)
|
||||
DEF (0xA8, SE_DBG_CTRL)
|
||||
DEF (0xA9, SE_DBG_DATA0)
|
||||
DEF (0xAA, SE_DBG_DATA1)
|
||||
DEF (0xAB, SE_DBG_DATA2)
|
||||
DEF (0xAC, SE_DBG_DATA3)
|
||||
DEF (0xAD, SE_WATCH)
|
||||
DEF (0xC0, BPU_BUILD)
|
||||
DEF (0xC1, ARC600_BUILD_CONFIG)
|
||||
DEF (0xC2, ISA_CONFIG)
|
||||
DEF (0xF4, HWP_BUILD)
|
||||
DEF (0xF5, PCT_BUILD)
|
||||
DEF (0xF6, CC_BUILD)
|
||||
DEF (0xF7, PM_BCR)
|
||||
DEF (0xF8, SCQ_SWITCH_BUILD)
|
||||
DEF (0xF9, VRAPTOR_BUILD)
|
||||
DEF (0xFA, DMA_CONFIG)
|
||||
DEF (0xFB, SIMD_CONFIG)
|
||||
DEF (0xFC, VLC_BUILD)
|
||||
DEF (0xFD, SIMD_DMA_BUILD)
|
||||
DEF (0xFE, IFETCH_QUEUE_BUILD)
|
||||
DEF (0xFF, SMART_BUILD)
|
||||
DEF (0x100, COUNT1)
|
||||
DEF (0x101, CONTROL1)
|
||||
DEF (0x101, CONTROL1)
|
||||
DEF (0x102, LIMIT1)
|
||||
DEF (0x103, TIMER_XX)
|
||||
DEF (0x120, ARCANGEL_PERIPH_XX)
|
||||
DEF (0x140, PERIPH_XX)
|
||||
DEF (0x200, AUX_IRQ_LEV)
|
||||
DEF (0x201, AUX_IRQ_HINT)
|
||||
DEF (0x202, AUX_INTER_CORE_INTERRUPT)
|
||||
DEF (0x210, AES_AUX_0)
|
||||
DEF (0x211, AES_AUX_1)
|
||||
DEF (0x212, AES_AUX_2)
|
||||
DEF (0x213, AES_CRYPT_MODE)
|
||||
DEF (0x214, AES_AUXS)
|
||||
DEF (0x215, AES_AUXI)
|
||||
DEF (0x216, AES_AUX_3)
|
||||
DEF (0x217, AES_AUX_4)
|
||||
DEF (0x218, ARITH_CTL_AUX)
|
||||
DEF (0x219, DES_AUX)
|
||||
DEF (0x220, AP_AMV0)
|
||||
DEF (0x221, AP_AMM0)
|
||||
DEF (0x222, AP_AC0)
|
||||
DEF (0x223, AP_AMV1)
|
||||
DEF (0x224, AP_AMM1)
|
||||
DEF (0x225, AP_AC1)
|
||||
DEF (0x226, AP_AMV2)
|
||||
DEF (0x227, AP_AMM2)
|
||||
DEF (0x228, AP_AC2)
|
||||
DEF (0x229, AP_AMV3)
|
||||
DEF (0x22A, AP_AMM3)
|
||||
DEF (0x22B, AP_AC3)
|
||||
DEF (0x22C, AP_AMV4)
|
||||
DEF (0x22D, AP_AMM4)
|
||||
DEF (0x22E, AP_AC4)
|
||||
DEF (0x22F, AP_AMV5)
|
||||
DEF (0x230, AP_AMM5)
|
||||
DEF (0x231, AP_AC5)
|
||||
DEF (0x232, AP_AMV6)
|
||||
DEF (0x233, AP_AMM6)
|
||||
DEF (0x234, AP_AC6)
|
||||
DEF (0x235, AP_AMV7)
|
||||
DEF (0x236, AP_AMM7)
|
||||
DEF (0x237, AP_AC7)
|
||||
DEF (0x240, CC_*)
|
||||
DEF (0x250, PCT_COUNT*)
|
||||
DEF (0x260, PCT_SNAP*)
|
||||
DEF (0x270, PCT_CONFIG*)
|
||||
DEF (0x278, PCT_CONTROL)
|
||||
DEF (0x279, PCT_BANK)
|
||||
DEF (0x300, FP_STATUS)
|
||||
DEF (0x300, RTT (A5 - A4))
|
||||
DEF (0x301, AUX_DPFP1L)
|
||||
DEF (0x301, RTT (A5 - A4))
|
||||
DEF (0x302, AUX_DPFP1H)
|
||||
DEF (0x302, RTT (A5 - A4))
|
||||
DEF (0x303, AUX_DPFP2L)
|
||||
DEF (0x303, RTT (A5 - A4))
|
||||
DEF (0x304, AUX_DPFP2H)
|
||||
DEF (0x304, RTT (A5 - A4))
|
||||
DEF (0x305, DPFP_STATUS)
|
||||
DEF (0x305, RTT (A5 - A4))
|
||||
DEF (0x306, RTT)
|
||||
DEF (0x400, ERET)
|
||||
DEF (0x401, ERBTA)
|
||||
DEF (0x402, ERSTATUS)
|
||||
DEF (0x403, ECR)
|
||||
DEF (0x404, EFA)
|
||||
DEF (0x405, TLBPD0)
|
||||
DEF (0x406, TLBPD1)
|
||||
DEF (0x407, TLBIndex)
|
||||
DEF (0x408, TLBCommand)
|
||||
DEF (0x409, PID)
|
||||
DEF (0x409, MPUEN)
|
||||
DEF (0x40A, ICAUSE1)
|
||||
DEF (0x40B, ICAUSE2)
|
||||
DEF (0x40C, AUX_IENABLE)
|
||||
DEF (0x40D, AUX_ITRIGGER)
|
||||
DEF (0x410, XPU)
|
||||
DEF (0x412, BTA)
|
||||
DEF (0x413, BTA_L1)
|
||||
DEF (0x414, BTA_L2)
|
||||
DEF (0x415, AUX_IRQ_PULSE_CANCEL)
|
||||
DEF (0x416, AUX_IRQ_PENDING)
|
||||
DEF (0x418, SCRATCH_DATA0)
|
||||
DEF (0x420, MPUIC)
|
||||
DEF (0x421, MPUFA)
|
||||
DEF (0x422, MPURDB0)
|
||||
DEF (0x423, MPURDP0)
|
||||
DEF (0x424, MPURDB1)
|
||||
DEF (0x425, MPURDP1)
|
||||
DEF (0x426, MPURDB2)
|
||||
DEF (0x427, MPURDP2)
|
||||
DEF (0x428, MPURDB3)
|
||||
DEF (0x429, MPURDP3)
|
||||
DEF (0x42A, MPURDB4)
|
||||
DEF (0x42B, MPURDP4)
|
||||
DEF (0x42C, MPURDB5)
|
||||
DEF (0x42D, MPURDP5)
|
||||
DEF (0x42E, MPURDB6)
|
||||
DEF (0x42F, MPURDP6)
|
||||
DEF (0x430, MPURDB7)
|
||||
DEF (0x431, MPURDP7)
|
||||
DEF (0x432, MPURDB8)
|
||||
DEF (0x433, MPURDP8)
|
||||
DEF (0x434, MPURDB9)
|
||||
DEF (0x435, MPURDP9)
|
||||
DEF (0x436, MPURDB10)
|
||||
DEF (0x437, MPURDP10)
|
||||
DEF (0x438, MPURDB11)
|
||||
DEF (0x439, MPURDP11)
|
||||
DEF (0x43A, MPURDB12)
|
||||
DEF (0x43B, MPURDP12)
|
||||
DEF (0x43C, MPURDB13)
|
||||
DEF (0x43D, MPURDP13)
|
||||
DEF (0x43E, MPURDB14)
|
||||
DEF (0x43F, MPURDP14)
|
||||
DEF (0x440, MPURDB15)
|
||||
DEF (0x441, MPURDP15)
|
||||
DEF (0x44F, EIA_FLAGS)
|
||||
DEF (0x450, PM_STATUS)
|
||||
DEF (0x451, WAKE)
|
||||
DEF (0x452, DVFS_PERFORMANCE)
|
||||
DEF (0x453, PWR_CTRL)
|
||||
DEF (0x500, AUX_VLC_BUF_IDX)
|
||||
DEF (0x501, AUX_VLC_READ_BUF)
|
||||
DEF (0x502, AUX_VLC_VALID_BITS)
|
||||
DEF (0x503, AUX_VLC_BUF_IN)
|
||||
DEF (0x504, AUX_VLC_BUF_FREE)
|
||||
DEF (0x505, AUX_VLC_IBUF_STATUS)
|
||||
DEF (0x506, AUX_VLC_SETUP)
|
||||
DEF (0x507, AUX_VLC_BITS)
|
||||
DEF (0x508, AUX_VLC_TABLE)
|
||||
DEF (0x509, AUX_VLC_GET_SYMBOL)
|
||||
DEF (0x50A, AUX_VLC_READ_SYMBOL)
|
||||
DEF (0x510, AUX_UCAVLC_SETUP)
|
||||
DEF (0x511, AUX_UCAVLC_STATE)
|
||||
DEF (0x512, AUX_CAVLC_ZERO_LEFT)
|
||||
DEF (0x514, AUX_UVLC_I_STATE)
|
||||
DEF (0x51C, AUX_VLC_DMA_PTR)
|
||||
DEF (0x51D, AUX_VLC_DMA_END)
|
||||
DEF (0x51E, AUX_VLC_DMA_ESC)
|
||||
DEF (0x51F, AUX_VLC_DMA_CTRL)
|
||||
DEF (0x520, AUX_VLC_GET_0BIT)
|
||||
DEF (0x521, AUX_VLC_GET_1BIT)
|
||||
DEF (0x522, AUX_VLC_GET_2BIT)
|
||||
DEF (0x523, AUX_VLC_GET_3BIT)
|
||||
DEF (0x524, AUX_VLC_GET_4BIT)
|
||||
DEF (0x525, AUX_VLC_GET_5BIT)
|
||||
DEF (0x526, AUX_VLC_GET_6BIT)
|
||||
DEF (0x527, AUX_VLC_GET_7BIT)
|
||||
DEF (0x528, AUX_VLC_GET_8BIT)
|
||||
DEF (0x529, AUX_VLC_GET_9BIT)
|
||||
DEF (0x52A, AUX_VLC_GET_10BIT)
|
||||
DEF (0x52B, AUX_VLC_GET_11BIT)
|
||||
DEF (0x52C, AUX_VLC_GET_12BIT)
|
||||
DEF (0x52D, AUX_VLC_GET_13BIT)
|
||||
DEF (0x52E, AUX_VLC_GET_14BIT)
|
||||
DEF (0x52F, AUX_VLC_GET_15BIT)
|
||||
DEF (0x530, AUX_VLC_GET_16BIT)
|
||||
DEF (0x531, AUX_VLC_GET_17BIT)
|
||||
DEF (0x532, AUX_VLC_GET_18BIT)
|
||||
DEF (0x533, AUX_VLC_GET_19BIT)
|
||||
DEF (0x534, AUX_VLC_GET_20BIT)
|
||||
DEF (0x535, AUX_VLC_GET_21BIT)
|
||||
DEF (0x536, AUX_VLC_GET_22BIT)
|
||||
DEF (0x537, AUX_VLC_GET_23BIT)
|
||||
DEF (0x538, AUX_VLC_GET_24BIT)
|
||||
DEF (0x539, AUX_VLC_GET_25BIT)
|
||||
DEF (0x53A, AUX_VLC_GET_26BIT)
|
||||
DEF (0x53B, AUX_VLC_GET_27BIT)
|
||||
DEF (0x53C, AUX_VLC_GET_28BIT)
|
||||
DEF (0x53D, AUX_VLC_GET_29BIT)
|
||||
DEF (0x53E, AUX_VLC_GET_30BIT)
|
||||
DEF (0x53F, AUX_VLC_GET_31BIT)
|
||||
DEF (0x540, AUX_CABAC_CTRL)
|
||||
DEF (0x541, AUX_CABAC_CTX_STATE)
|
||||
DEF (0x542, AUX_CABAC_COD_PARAM)
|
||||
DEF (0x543, AUX_CABAC_MISC0)
|
||||
DEF (0x544, AUX_CABAC_MISC1)
|
||||
DEF (0x545, AUX_CABAC_MISC2)
|
||||
DEF (0x600, ARC600_BUILD_CONFIG)
|
||||
DEF (0x700, SMART_CONTROL)
|
||||
DEF (0x701, SMART_DATA_0)
|
||||
DEF (0x701, SMART_DATA_1)
|
||||
DEF (0x701, SMART_DATA_2)
|
||||
DEF (0x701, SMART_DATA_3)
|
||||
18198
opcodes/arc-tbl.h
Normal file
18198
opcodes/arc-tbl.h
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user