forked from Imagelibrary/binutils-gdb
cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes
This patch adds semantic RTL descriptions to the eBPF instructions defined in cpu/bpf.cpu. It also contains a couple of minor improvements. Tested in bpf-unknown-none targets. No regressions. cpu/ChangeLog: 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> * bpf.cpu (define-alu-insn-un): Add definitions of semantics. (define-alu-insn-mov): Likewise. (daib): Likewise. (define-alu-instructions): Likewise. (define-endian-insn): Likewise. (define-lddw): Likewise. (dlabs): Likewise. (dlind): Likewise. (dxli): Likewise. (dxsi): Likewise. (dsti): Likewise. (define-ldstx-insns): Likewise. (define-st-insns): Likewise. (define-cond-jump-insn): Likewise. (dcji): Likewise. (define-condjump-insns): Likewise. (define-call-insn): Likewise. (ja): Likewise. ("exit"): Likewise. (define-atomic-insns): Likewise. (sem-exchange-and-add): New macro. * bpf.cpu ("brkpt"): New instruction. (bpfbf): Set word-bitsize to 32 and insn-endian big. (h-gpr): Prefer r0 to `a' and r6 to `ctx'. (h-pc): Expand definition. * bpf.opc (bpf_print_insn): Set endian_code to BIG. opcodes/ChangeLog: 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.h: Likewise. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
This commit is contained in:
Jose E. Marchesi
@@ -1,3 +1,33 @@
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2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
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David Faust <david.faust@oracle.com>
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* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
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(define-alu-insn-mov): Likewise.
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(daib): Likewise.
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(define-alu-instructions): Likewise.
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(define-endian-insn): Likewise.
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(define-lddw): Likewise.
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(dlabs): Likewise.
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(dlind): Likewise.
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(dxli): Likewise.
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(dxsi): Likewise.
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(dsti): Likewise.
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(define-ldstx-insns): Likewise.
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(define-st-insns): Likewise.
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(define-cond-jump-insn): Likewise.
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(dcji): Likewise.
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(define-condjump-insns): Likewise.
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(define-call-insn): Likewise.
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(ja): Likewise.
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("exit"): Likewise.
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(define-atomic-insns): Likewise.
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(sem-exchange-and-add): New macro.
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* bpf.cpu ("brkpt"): New instruction.
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(bpfbf): Set word-bitsize to 32 and insn-endian big.
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(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
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(h-pc): Expand definition.
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* bpf.opc (bpf_print_insn): Set endian_code to BIG.
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2020-05-21 Alan Modra <amodra@gmail.com>
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* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
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328
cpu/bpf.cpu
328
cpu/bpf.cpu
@@ -32,6 +32,10 @@
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(name bpf)
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(comment "Linux kernel BPF")
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(insn-lsb0? #t)
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;; XXX explain the default-alignment setting is for the simulator.
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;; It is confusing that the simulator follows the emulated memory
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;; access conventions for fetching instructions by pieces...
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(default-alignment unaligned)
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(machs bpf)
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(isas ebpfle ebpfbe))
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@@ -121,7 +125,8 @@
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(define-cpu
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(name bpfbf)
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(comment "Linux kernel eBPF virtual CPU")
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(word-bitsize 32))
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(insn-endian big)
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(word-bitsize 64))
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(define-mach
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(name bpf)
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@@ -159,13 +164,19 @@
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(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
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(r7 7) (r8 8) (r9 9) (fp 10)
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;; Additional names recognized when assembling.
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(a 0) (ctx 6) (r10 10))))
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(r0 0) (r6 6) (r10 10))))
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;; The program counter. CGEN requires it, even if it is not visible
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;; to eBPF programs.
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(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
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(define-hardware
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(name h-pc)
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(comment "program counter")
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(attrs PC PROFILE all-isas)
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(type pc UDI)
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(get () (raw-reg h-pc))
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(set (newval) (set (raw-reg h-pc) newval)))
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;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
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;; shouldn't be needed, as h-sint is supposed to be able to hold
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;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
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@@ -361,60 +372,101 @@
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;; ADD[32]{i,r}le for the little-endian ISA
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;; ADD[32]{i,r}be for the big-endian ISA
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;;
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;; The `i' variants perform `src OP dst -> dst' operations.
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;; The `r' variants perform `dst OP imm32 -> dst' operations.
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;; The `i' variants perform `dst OP imm32 -> dst' operations.
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;; The `r' variants perform `dst OP src -> dst' operations.
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;;
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;; The variants with 32 in their name are of ALU class. Otherwise
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;; they are ALU64 class.
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(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code x-endian)
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(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
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x-endian x-mode x-semop)
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(dni (.sym x-basename x-suffix x-endian)
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(.str x-basename x-suffix)
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian)
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(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code) () ()))
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
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()))
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(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
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(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
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x-endian x-mode x-semop)
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(begin
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;; dst = dst OP immediate
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(dni (.sym x-basename x-suffix "i" x-endian)
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(.str x-basename x-suffix " immediate")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$imm32")
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(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code) () ())
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
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())
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;; dst = dst OP src
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(dni (.sym x-basename x-suffix "r" x-endian)
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(.str x-basename x-suffix " register")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
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(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
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x-op-class OP_SRC_X x-op-code) () ())))
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x-op-class OP_SRC_X x-op-code)
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(set x-mode (.sym dst x-endian)
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(x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
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())))
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(define-pmacro (daiu x-basename x-op-code x-endian)
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(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
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x-endian x-mode)
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(begin
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(define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
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(define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
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(dni (.sym mov x-suffix "i" x-endian)
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(.str mov x-suffix " immediate")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$imm32")
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(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) imm32)
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())
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(dni (.sym mov x-suffix "r" x-endian)
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(.str mov x-suffix " register")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
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(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
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x-op-class OP_SRC_X x-op-code)
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(set x-mode (.sym dst x-endian) (.sym src x-endian))
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())))
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(define-pmacro (daib x-basename x-op-code x-endian)
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;; Unary ALU instructions (neg)
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(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
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(begin
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(define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
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(define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
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(define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
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(define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
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;; Binary ALU instructions (all the others)
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;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
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(define-pmacro (daib x-basename x-op-code x-endian x-semop)
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(begin
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(define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
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(define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
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;; Move ALU instructions (mov)
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(define-pmacro (daim x-basename x-op-code x-endian)
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(begin
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(define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
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(define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
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(define-pmacro (define-alu-instructions x-endian)
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(begin
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(daib add OP_CODE_ADD x-endian)
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(daib sub OP_CODE_SUB x-endian)
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(daib mul OP_CODE_MUL x-endian)
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(daib div OP_CODE_DIV x-endian)
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(daib or OP_CODE_OR x-endian)
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(daib and OP_CODE_AND x-endian)
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(daib lsh OP_CODE_LSH x-endian)
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(daib rsh OP_CODE_RSH x-endian)
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(daib mod OP_CODE_MOD x-endian)
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(daib xor OP_CODE_XOR x-endian)
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(daib mov OP_CODE_MOV x-endian)
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(daib arsh OP_CODE_ARSH x-endian)
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(daiu neg OP_CODE_NEG x-endian)))
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(daib add OP_CODE_ADD x-endian add)
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(daib sub OP_CODE_SUB x-endian sub)
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(daib mul OP_CODE_MUL x-endian mul)
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(daib div OP_CODE_DIV x-endian div)
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(daib or OP_CODE_OR x-endian or)
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(daib and OP_CODE_AND x-endian and)
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(daib lsh OP_CODE_LSH x-endian sll)
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(daib rsh OP_CODE_RSH x-endian srl)
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(daib mod OP_CODE_MOD x-endian mod)
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(daib xor OP_CODE_XOR x-endian xor)
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(daib arsh OP_CODE_ARSH x-endian sra)
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(daiu neg OP_CODE_NEG x-endian neg)
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(daim mov OP_CODE_MOV x-endian)))
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(define-alu-instructions le)
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(define-alu-instructions be)
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@@ -438,7 +490,10 @@
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((ISA (.sym ebpf x-endian)))
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(.str "end" x-suffix " $dst" x-endian ",$endsize")
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(+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
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OP_CLASS_ALU x-op-src OP_CODE_END) () ()))
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OP_CLASS_ALU x-op-src OP_CODE_END)
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(set (.sym dst x-endian)
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(c-call DI "bpfbf_end" (.sym dst x-endian) endsize))
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()))
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(define-endian-insn "le" OP_SRC_K le)
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(define-endian-insn "be" OP_SRC_X le)
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@@ -461,7 +516,9 @@
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(.str "lddw $dst" x-endian ",$imm64")
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(+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
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(.sym dst x-endian)
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OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) () ()))
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OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
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(set DI (.sym dst x-endian) imm64)
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()))
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(define-lddw le)
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(define-lddw be)
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@@ -471,19 +528,33 @@
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;;
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;; LDABS{w,h,b,dw}
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(define-pmacro (dlabs x-suffix x-size)
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(define-pmacro (dlabs x-suffix x-size x-smode)
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(dni (.sym "ldabs" x-suffix)
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(.str "ldabs" x-suffix)
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(all-isas)
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(.str "ldabs" x-suffix " $imm32")
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(+ imm32 (f-offset16 0) (f-regs 0)
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OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
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() ()))
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(set x-smode
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(reg x-smode h-gpr 0)
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(mem x-smode
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(add DI
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(mem DI
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(add DI
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(reg DI h-gpr 6) ;; Pointer to struct sk_buff
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(const DI 0))) ;; XXX offsetof
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;; (struct sk_buff, data) XXX but the offset
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;; depends on CONFIG_* options, so this should
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;; be configured in the simulator and driven by
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;; command-line options. Handle with a c-call.
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imm32)))
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;; XXX this clobbers R1-R5
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()))
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(dlabs "w" W)
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(dlabs "h" H)
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(dlabs "b" B)
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(dlabs "dw" DW)
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(dlabs "w" W SI)
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(dlabs "h" H HI)
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(dlabs "b" B QI)
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(dlabs "dw" DW DI)
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;; The indirect load instructions are non-generic loads designed to be
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;; used in socket filters. They come in several variants:
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@@ -491,21 +562,37 @@
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;; LDIND{w,h,b,dw}le for the little-endian ISA
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;; LDIND[w,h,b,dw}be for the big-endian ISA
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(define-pmacro (dlind x-suffix x-size x-endian)
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(define-pmacro (dlind x-suffix x-size x-endian x-smode)
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(dni (.sym "ldind" x-suffix x-endian)
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(.str "ldind" x-suffix)
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((ISA (.sym ebpf x-endian)))
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(.str "ldind" x-suffix " $src" x-endian ",$imm32")
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(+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
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OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
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() ()))
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(set x-smode
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(reg x-smode h-gpr 0)
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(mem x-smode
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(add DI
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(mem DI
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(add DI
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(reg DI h-gpr 6) ;; Pointer to struct sk_buff
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(const DI 0))) ;; XXX offsetof
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;; (struct sk_buff, data) XXX but the offset
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;; depends on CONFIG_* options, so this should
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;; be configured in the simulator and driven by
|
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;; command-line options. Handle with a c-call.
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(add DI
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(.sym src x-endian)
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imm32))))
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;; XXX this clobbers R1-R5
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()))
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(define-pmacro (define-ldind x-endian)
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(begin
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(dlind "w" W x-endian)
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(dlind "h" H x-endian)
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(dlind "b" B x-endian)
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(dlind "dw" DW x-endian)))
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(dlind "w" W x-endian SI)
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(dlind "h" H x-endian HI)
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(dlind "b" B x-endian QI)
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(dlind "dw" DW x-endian DI)))
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(define-ldind le)
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(define-ldind be)
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@@ -520,35 +607,41 @@
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;; Loads operate on [$SRC+-OFFSET] -> $DST
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;; Stores operate on $SRC -> [$DST+-OFFSET]
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(define-pmacro (dxli x-basename x-suffix x-size x-endian)
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(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
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(dni (.sym x-basename x-suffix x-endian)
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(.str x-basename x-suffix)
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
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(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
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OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
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||||
() ()))
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||||
(set x-mode
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(.sym dst x-endian)
|
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(mem x-mode (add DI (.sym src x-endian) (ext DI (trunc HI offset16)))))
|
||||
()))
|
||||
|
||||
(define-pmacro (dxsi x-basename x-suffix x-size x-endian)
|
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(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
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||||
(dni (.sym x-basename x-suffix x-endian)
|
||||
(.str x-basename x-suffix)
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
|
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(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
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||||
OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
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() ()))
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||||
(set x-mode
|
||||
(mem x-mode (add DI (.sym dst x-endian) (ext DI (trunc HI offset16))))
|
||||
(.sym src x-endian)) ;; XXX address is section-relative
|
||||
()))
|
||||
|
||||
(define-pmacro (define-ldstx-insns x-endian)
|
||||
(begin
|
||||
(dxli "ldx" "w" W x-endian)
|
||||
(dxli "ldx" "h" H x-endian)
|
||||
(dxli "ldx" "b" B x-endian)
|
||||
(dxli "ldx" "dw" DW x-endian)
|
||||
(dxli "ldx" "w" W x-endian SI)
|
||||
(dxli "ldx" "h" H x-endian HI)
|
||||
(dxli "ldx" "b" B x-endian QI)
|
||||
(dxli "ldx" "dw" DW x-endian DI)
|
||||
|
||||
(dxsi "stx" "w" W x-endian)
|
||||
(dxsi "stx" "h" H x-endian)
|
||||
(dxsi "stx" "b" B x-endian)
|
||||
(dxsi "stx" "dw" DW x-endian)))
|
||||
(dxsi "stx" "w" W x-endian SI)
|
||||
(dxsi "stx" "h" H x-endian HI)
|
||||
(dxsi "stx" "b" B x-endian QI)
|
||||
(dxsi "stx" "dw" DW x-endian DI)))
|
||||
|
||||
(define-ldstx-insns le)
|
||||
(define-ldstx-insns be)
|
||||
@@ -559,20 +652,24 @@
|
||||
;; ST{b,h,w,dw}le for the little-endian ISA
|
||||
;; ST{b,h,w,dw}be for the big-endian ISA
|
||||
|
||||
(define-pmacro (dsti x-suffix x-size x-endian)
|
||||
(define-pmacro (dsti x-suffix x-size x-endian x-mode)
|
||||
(dni (.sym "st" x-suffix x-endian)
|
||||
(.str "st" x-suffix)
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
|
||||
(+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
|
||||
OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) () ()))
|
||||
OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
|
||||
(set x-mode
|
||||
(mem x-mode (add DI (.sym dst x-endian) offset16))
|
||||
imm32) ;; XXX address is section-relative
|
||||
()))
|
||||
|
||||
(define-pmacro (define-st-insns x-endian)
|
||||
(begin
|
||||
(dsti "b" B x-endian)
|
||||
(dsti "h" H x-endian)
|
||||
(dsti "w" W x-endian)
|
||||
(dsti "dw" DW x-endian)))
|
||||
(dsti "b" B x-endian QI)
|
||||
(dsti "h" H x-endian HI)
|
||||
(dsti "w" W x-endian SI)
|
||||
(dsti "dw" DW x-endian DI)))
|
||||
|
||||
(define-st-insns le)
|
||||
(define-st-insns be)
|
||||
@@ -588,64 +685,102 @@
|
||||
;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
|
||||
;; big-endian ISA.
|
||||
|
||||
(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
|
||||
(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
|
||||
(begin
|
||||
(dni (.sym j x-cond x-suffix i x-endian)
|
||||
(.str j x-cond x-suffix " i")
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
|
||||
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
|
||||
x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
|
||||
x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
|
||||
(if VOID (x-semop x-mode (.sym dst x-endian) imm32)
|
||||
(set DI
|
||||
(reg DI h-pc) (add DI (reg DI h-pc)
|
||||
(mul DI (add HI disp16 1) 8))))
|
||||
())
|
||||
(dni (.sym j x-cond x-suffix r x-endian)
|
||||
(.str j x-cond x-suffix " r")
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
|
||||
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
|
||||
x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
|
||||
x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
|
||||
(if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
|
||||
(set DI
|
||||
(reg DI h-pc) (add DI (reg DI h-pc)
|
||||
(mul DI (add HI disp16 1) 8))))
|
||||
())))
|
||||
|
||||
(define-pmacro (dcji x-cond x-op-code x-endian)
|
||||
(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
|
||||
(begin
|
||||
(define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
|
||||
(define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
|
||||
(define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
|
||||
(define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
|
||||
|
||||
(define-pmacro (define-condjump-insns x-endian)
|
||||
(begin
|
||||
(dcji "eq" JEQ x-endian)
|
||||
(dcji "gt" JGT x-endian)
|
||||
(dcji "ge" JGE x-endian)
|
||||
(dcji "lt" JLT x-endian)
|
||||
(dcji "le" JLE x-endian)
|
||||
(dcji "set" JSET x-endian)
|
||||
(dcji "ne" JNE x-endian)
|
||||
(dcji "sgt" JSGT x-endian)
|
||||
(dcji "sge" JSGE x-endian)
|
||||
(dcji "slt" JSLT x-endian)
|
||||
(dcji "sle" JSLE x-endian)))
|
||||
(dcji "eq" JEQ x-endian eq)
|
||||
(dcji "gt" JGT x-endian gtu)
|
||||
(dcji "ge" JGE x-endian geu)
|
||||
(dcji "lt" JLT x-endian ltu)
|
||||
(dcji "le" JLE x-endian leu)
|
||||
(dcji "set" JSET x-endian and)
|
||||
(dcji "ne" JNE x-endian ne)
|
||||
(dcji "sgt" JSGT x-endian gt)
|
||||
(dcji "sge" JSGE x-endian ge)
|
||||
(dcji "slt" JSLT x-endian lt)
|
||||
(dcji "sle" JSLE x-endian le)))
|
||||
|
||||
(define-condjump-insns le)
|
||||
(define-condjump-insns be)
|
||||
|
||||
;; The jump-always, `call' and `exit' instructions dont make use of
|
||||
;; either source nor destination registers, so only one variant per
|
||||
;; The `call' instruction doesn't make use of registers, but the
|
||||
;; semantic routine should have access to the src register in order to
|
||||
;; properly interpret the meaning of disp32. Therefore we need one
|
||||
;; version per ISA.
|
||||
|
||||
(define-pmacro (define-call-insn x-endian)
|
||||
(dni (.sym call x-endian)
|
||||
"call"
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
"call $disp32"
|
||||
(+ disp32 (f-offset16 0) (f-regs 0)
|
||||
OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
|
||||
(c-call VOID
|
||||
"bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
|
||||
()))
|
||||
|
||||
(define-call-insn le)
|
||||
(define-call-insn be)
|
||||
|
||||
;; The jump-always and `exit' instructions dont make use of either
|
||||
;; source nor destination registers, so only one variant per
|
||||
;; instruction is defined.
|
||||
|
||||
(dni ja "ja" (all-isas) "ja $disp16"
|
||||
(+ (f-imm32 0) disp16 (f-regs 0)
|
||||
OP_CLASS_JMP OP_SRC_K OP_CODE_JA) () ())
|
||||
|
||||
(dni call "call" (all-isas) "call $disp32"
|
||||
(+ disp32 (f-offset16 0) (f-regs 0)
|
||||
OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) () ())
|
||||
OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
|
||||
(set DI (reg DI h-pc) (add DI (reg DI h-pc)
|
||||
(mul DI (add HI disp16 1) 8)))
|
||||
())
|
||||
|
||||
(dni "exit" "exit" (all-isas) "exit"
|
||||
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
|
||||
OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) () ())
|
||||
OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
|
||||
(c-call VOID "bpfbf_exit")
|
||||
())
|
||||
|
||||
;;; Atomic instructions
|
||||
|
||||
;; The atomic exchange-and-add instructions come in two flavors: one
|
||||
;; for swapping 64-bit quantities and another for 32-bit quantities.
|
||||
|
||||
(define-pmacro (sem-exchange-and-add x-endian x-mode)
|
||||
(sequence VOID ((x-mode tmp))
|
||||
;; XXX acquire lock in simulator... as a hardware element?
|
||||
(set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
|
||||
(set x-mode
|
||||
(mem x-mode (add DI (.sym dst x-endian) offset16))
|
||||
(add x-mode tmp (.sym src x-endian)))))
|
||||
|
||||
(define-pmacro (define-atomic-insns x-endian)
|
||||
(begin
|
||||
(dni (.str "xadddw" x-endian)
|
||||
@@ -653,13 +788,28 @@
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
|
||||
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
|
||||
offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) () ())
|
||||
offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
|
||||
(sem-exchange-and-add x-endian DI)
|
||||
())
|
||||
(dni (.str "xaddw" x-endian)
|
||||
"xaddw"
|
||||
((ISA (.sym ebpf x-endian)))
|
||||
(.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
|
||||
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
|
||||
offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) () ())))
|
||||
offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
|
||||
(sem-exchange-and-add x-endian SI)
|
||||
())))
|
||||
|
||||
(define-atomic-insns le)
|
||||
(define-atomic-insns be)
|
||||
|
||||
;;; Breakpoint instruction
|
||||
|
||||
;; The brkpt instruction is used by the BPF simulator and it doesn't
|
||||
;; really belong to the eBPF instruction set.
|
||||
|
||||
(dni "brkpt" "brkpt" (all-isas) "brkpt"
|
||||
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
|
||||
OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
|
||||
(c-call VOID "bpfbf_breakpoint")
|
||||
())
|
||||
|
||||
@@ -129,6 +129,7 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
|
||||
info->bytes_per_chunk = 1;
|
||||
info->bytes_per_line = 8;
|
||||
info->endian_code = BFD_ENDIAN_BIG;
|
||||
|
||||
/* Attempt to read the base part of the insn. */
|
||||
buflen = cd->base_insn_bitsize / 8;
|
||||
|
||||
Reference in New Issue
Block a user