forked from Imagelibrary/binutils-gdb
bfd:
* elf32-tic6x.c (elf32_tic6x_merge_arch_attributes): Update for attribute renaming. (elf_backend_obj_attrs_section): Change to ".c6xabi.attributes". binutils: * readelf.c (display_tic6x_attribute): Update for attribute renaming. gas: * config/tc-tic6x.c (tic6x_arch_attribute, tic6x_arches, md_assemble, tic6x_set_attributes): Update for attribute renaming. * doc/c-tic6x.texi: Update for attribute renaming. gas/testsuite: * gas/tic6x/attr-arch-directive-1.d, gas/tic6x/attr-arch-directive-2.d, gas/tic6x/attr-arch-directive-3.d, gas/tic6x/attr-arch-directive-4.d, gas/tic6x/attr-arch-directive-4.s, gas/tic6x/attr-arch-directive-5.d, gas/tic6x/attr-arch-directive-5.s, gas/tic6x/attr-arch-opts-c62x.d, gas/tic6x/attr-arch-opts-c64x+.d, gas/tic6x/attr-arch-opts-c64x.d, gas/tic6x/attr-arch-opts-c674x.d, gas/tic6x/attr-arch-opts-c67x+.d, gas/tic6x/attr-arch-opts-c67x.d, gas/tic6x/attr-arch-opts-none-1.d, gas/tic6x/attr-arch-opts-none-2.d, gas/tic6x/attr-arch-opts-override-1.d, gas/tic6x/attr-arch-opts-override-2.d: Update for attribute renaming and renumbering. include/elf: * tic6x-attrs.h (Tag_C6XABI_Tag_CPU_arch): Change to Tag_ISA, value 4. * tic6x.h (Values for Tag_C6XABI_Tag_CPU_arch): Rename for attribute renaming. ld: * emulparams/elf32_tic6x_le.sh (ATTRS_SECTIONS): Use .c6xabi.attributes, not __TI_build_attributes. ld/testsuite: * ld-tic6x/attr-arch-c62x-c62x.d, ld-tic6x/attr-arch-c62x-c64x+.d, ld-tic6x/attr-arch-c62x-c64x.d, ld-tic6x/attr-arch-c62x-c674x.d, ld-tic6x/attr-arch-c62x-c67x+.d, ld-tic6x/attr-arch-c62x-c67x.d, ld-tic6x/attr-arch-c64x+-c62x.d, ld-tic6x/attr-arch-c64x+-c64x+.d, ld-tic6x/attr-arch-c64x+-c64x.d, ld-tic6x/attr-arch-c64x+-c674x.d, ld-tic6x/attr-arch-c64x+-c67x+.d, ld-tic6x/attr-arch-c64x+-c67x.d, ld-tic6x/attr-arch-c64x-c62x.d, ld-tic6x/attr-arch-c64x-c64x+.d, ld-tic6x/attr-arch-c64x-c64x.d, ld-tic6x/attr-arch-c64x-c674x.d, ld-tic6x/attr-arch-c64x-c67x+.d, ld-tic6x/attr-arch-c64x-c67x.d, ld-tic6x/attr-arch-c674x-c62x.d, ld-tic6x/attr-arch-c674x-c64x+.d, ld-tic6x/attr-arch-c674x-c64x.d, ld-tic6x/attr-arch-c674x-c674x.d, ld-tic6x/attr-arch-c674x-c67x+.d, ld-tic6x/attr-arch-c674x-c67x.d, ld-tic6x/attr-arch-c67x+-c62x.d, ld-tic6x/attr-arch-c67x+-c64x+.d, ld-tic6x/attr-arch-c67x+-c64x.d, ld-tic6x/attr-arch-c67x+-c674x.d, ld-tic6x/attr-arch-c67x+-c67x+.d, ld-tic6x/attr-arch-c67x+-c67x.d, ld-tic6x/attr-arch-c67x-c62x.d, ld-tic6x/attr-arch-c67x-c64x+.d, ld-tic6x/attr-arch-c67x-c64x.d, ld-tic6x/attr-arch-c67x-c674x.d, ld-tic6x/attr-arch-c67x-c67x+.d, ld-tic6x/attr-arch-c67x-c67x.d: Update for attribute renaming.
This commit is contained in:
@@ -82,9 +82,9 @@ static unsigned short tic6x_arch_enable = (TIC6X_INSN_C62X
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(architecture, as modified by other options). */
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static unsigned short tic6x_features;
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/* The architecture attribute value, or C6XABI_Tag_CPU_arch_none if
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/* The architecture attribute value, or C6XABI_Tag_ISA_none if
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not yet set. */
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static int tic6x_arch_attribute = C6XABI_Tag_CPU_arch_none;
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static int tic6x_arch_attribute = C6XABI_Tag_ISA_none;
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/* Whether any instructions at all have been seen. Once any
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instructions have been seen, architecture attributes merge into the
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@@ -120,21 +120,21 @@ typedef struct
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} tic6x_arch_table;
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static const tic6x_arch_table tic6x_arches[] =
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{
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{ "c62x", C6XABI_Tag_CPU_arch_C62X, TIC6X_INSN_C62X },
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{ "c64x", C6XABI_Tag_CPU_arch_C64X, TIC6X_INSN_C62X | TIC6X_INSN_C64X },
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{ "c64x+", C6XABI_Tag_CPU_arch_C64XP, (TIC6X_INSN_C62X
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| TIC6X_INSN_C64X
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| TIC6X_INSN_C64XP) },
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{ "c67x", C6XABI_Tag_CPU_arch_C67X, TIC6X_INSN_C62X | TIC6X_INSN_C67X },
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{ "c67x+", C6XABI_Tag_CPU_arch_C67XP, (TIC6X_INSN_C62X
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| TIC6X_INSN_C67X
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| TIC6X_INSN_C67XP) },
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{ "c674x", C6XABI_Tag_CPU_arch_C674X, (TIC6X_INSN_C62X
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| TIC6X_INSN_C64X
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| TIC6X_INSN_C64XP
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| TIC6X_INSN_C67X
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| TIC6X_INSN_C67XP
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| TIC6X_INSN_C674X) }
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{ "c62x", C6XABI_Tag_ISA_C62X, TIC6X_INSN_C62X },
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{ "c64x", C6XABI_Tag_ISA_C64X, TIC6X_INSN_C62X | TIC6X_INSN_C64X },
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{ "c64x+", C6XABI_Tag_ISA_C64XP, (TIC6X_INSN_C62X
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| TIC6X_INSN_C64X
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| TIC6X_INSN_C64XP) },
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{ "c67x", C6XABI_Tag_ISA_C67X, TIC6X_INSN_C62X | TIC6X_INSN_C67X },
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{ "c67x+", C6XABI_Tag_ISA_C67XP, (TIC6X_INSN_C62X
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| TIC6X_INSN_C67X
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| TIC6X_INSN_C67XP) },
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{ "c674x", C6XABI_Tag_ISA_C674X, (TIC6X_INSN_C62X
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| TIC6X_INSN_C64X
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| TIC6X_INSN_C64XP
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| TIC6X_INSN_C67X
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| TIC6X_INSN_C67XP
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| TIC6X_INSN_C674X) }
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};
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/* Update the selected architecture based on ARCH, giving an error if
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@@ -2685,8 +2685,8 @@ md_assemble (char *str)
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/* If no .arch directives or -march options have been seen, we are
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assessing instruction validity based on the C674X default, so set
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the attribute accordingly. */
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if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
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tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
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if (tic6x_arch_attribute == C6XABI_Tag_ISA_none)
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tic6x_arch_attribute = C6XABI_Tag_ISA_C674X;
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/* Reset global settings for parallel bars and predicates now to
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avoid extra errors if there are problems with this opcode. */
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@@ -3891,10 +3891,10 @@ tic6x_set_attribute_int (int tag, int value)
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static void
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tic6x_set_attributes (void)
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{
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if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
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tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
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if (tic6x_arch_attribute == C6XABI_Tag_ISA_none)
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tic6x_arch_attribute = C6XABI_Tag_ISA_C674X;
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tic6x_set_attribute_int (Tag_C6XABI_Tag_CPU_arch, tic6x_arch_attribute);
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tic6x_set_attribute_int (Tag_ISA, tic6x_arch_attribute);
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}
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/* Do machine-dependent manipulations of the frag chains after all
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