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Remove support for the (deprecated) openrisc and or32 configurations and replace

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with support for the new or1k configuration.
This commit is contained in:
Christian Svensson
2014-04-22 15:57:47 +01:00
committed by Nick Clifton
parent a75fef0e5b
commit 73589c9dbd
135 changed files with 12474 additions and 9221 deletions
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10
cpu/ChangeLog
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@@ -1,3 +1,13 @@
2014-04-22 Christian Svensson <blue@cmd.nu>
* openrisc.cpu: Delete.
* openrisc.opc: Delete.
* or1k.cpu: New file.
* or1k.opc: New file.
* or1kcommon.cpu: New file.
* or1korbis.cpu: New file.
* or1korfpx.cpu: New file.
2013-12-07 Mike Frysinger <vapier@gentoo.org>
* epiphany.opc: Remove +x file mode.

774
cpu/openrisc.cpu
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@@ -1,774 +0,0 @@
; OpenRISC family. -*- Scheme -*-
; Copyright 2000, 2001, 2011 Free Software Foundation, Inc.
; Contributed by Johan Rydberg, jrydberg@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
(include "simplify.inc")
; OpenRISC 1000 is an architecture of a family of open source,
; synthesizeable RISC microprocessor cores. It is a 32-bit load
; and store RISC architecture designed with emphasis on speed,
; compact instruction set and scalability. OpenRISC 1000 targets
; wide range of embedded environments.
(define-arch
(name openrisc)
(comment "OpenRISC 1000")
(insn-lsb0? #t)
(machs openrisc or1300)
(isas or32)
)
; Attributes
; An attribute to describe if a model has insn and/or data caches.
(define-attr
(for model)
(type enum)
(name HAS-CACHE)
(comment "if this model has caches")
(values DATA-CACHE INSN-CACHE)
)
; An attribute to describe if an insn can be in the delay slot or not.
(define-attr
(for insn)
(type boolean)
(name NOT-IN-DELAY-SLOT)
(comment "insn can't go in delay slot")
)
; IDOC attribute for instruction documentation.
(define-attr
(for insn)
(type enum)
(name IDOC)
(comment "insn kind for documentation")
(attrs META)
(values
(MEM - () "Memory")
(ALU - () "ALU")
(FPU - () "FPU")
(BR - () "Branch")
(PRIV - () "Priviledged")
(MISC - () "Miscellaneous")
)
)
; Enum for exception vectors.
(define-enum
(name e-exception)
(comment "exception vectors")
(attrs)
(prefix E_)
(values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -)
("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -)
("SYSCALL" -) ("BREAK" -) ("RESERVED" -)))
)
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name or32)
; Base insturction length. The insns is always 32 bits wide.
(base-insn-bitsize 32)
; Address of insn in delay slot
(setup-semantics (set-quiet (reg h-delay-insn) (add pc 4)))
)
; CPU family definitions.
(define-cpu
; CPU names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name openriscbf)
(comment "OpenRISC base family")
(endian big)
(word-bitsize 32)
)
; Generic machine
(define-mach
(name openrisc)
(comment "Generic OpenRISC cpu")
(cpu openriscbf)
(bfd-name "openrisc")
)
; OpenRISC 1300 machine
(define-mach
(name or1300)
(comment "OpenRISC 1300")
(cpu openriscbf)
(bfd-name "openrisc:1300")
)
; Model descriptions
; Generic OpenRISC model
(define-model
(name openrisc-1) (comment "OpenRISC generic model") (attrs)
(mach openrisc)
; Nothing special about this.
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; OpenRISC 1320
(define-model
(name or1320-1) (comment "OpenRISC 1320 model")
; This model has both instruction and data cache
(attrs (HAS-CACHE INSN-CACHE,DATA-CACHE))
(mach or1300)
; Nothing special about this.
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; Instruction fields.
; Attributes:
; . PCREL-ADDR pc relative value (for reloc and disassembly purposes)
; . ABS-ADDR absolute address (for reloc and disassembly purposes?)
; . RESERVED bits are not used to decode insn, must be all 0
; Instruction classes.
(dnf f-class "insn class" () 31 2)
(dnf f-sub "sub class" () 29 4)
; Register fields.
(dnf f-r1 "r1" () 25 5)
(dnf f-r2 "r2" () 20 5)
(dnf f-r3 "r3" () 15 5)
; Immediates.
(df f-simm16 "signed imm (16)" () 15 16 INT #f #f)
(dnf f-uimm16 "unsigned imm (16)" () 15 16)
(dnf f-uimm5 "unsigned imm (5)" () 4 5)
(df f-hi16 "high 16" () 15 16 INT #f #f)
(df f-lo16 "low 16" () 15 16 INT #f #f)
; Sub fields
(dnf f-op1 "op1" () 31 2)
(dnf f-op2 "op2" () 29 4)
(dnf f-op3 "op3" () 25 2)
(dnf f-op4 "op4" () 23 3)
(dnf f-op5 "op3" () 25 5)
(dnf f-op6 "op4" () 7 3)
(dnf f-op7 "op5" () 3 4)
(dnf f-i16-1 "uimm16-1" () 10 11)
(dnf f-i16-2 "uimm16-2" () 25 5)
; PC relative, 26-bit (2 shifted to right)
(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc)))
; absolute, 26-bit (2 shifted to right)
(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT
((value pc) (sra WI pc (const 2)))
((value pc) (sll WI value (const 2))))
(define-multi-ifield
(name f-i16nc)
(comment "16 bit signed")
(attrs SIGN-OPT)
(mode HI)
(subfields f-i16-1 f-i16-2)
(insert (sequence ()
(set (ifield f-i16-2) (and (sra (ifield f-i16nc)
(const 11))
(const #x1f)))
(set (ifield f-i16-1) (and (ifield f-i16nc)
(const #x7ff)))))
(extract (sequence ()
(set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit"
(or (sll (ifield f-i16-2)
(const 11))
(ifield f-i16-1))))))
)
; Enums.
; insn-class: bits 31-30
(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class
(.map .str (.iota 4))
)
(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub
(.map .str (.iota 16))
)
(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3
(.map .str (.iota 4))
)
(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4
(.map .str (.iota 8))
)
(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5
(.map .str (.iota 32))
)
(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6
(.map .str (.iota 8))
)
(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7
(.map .str (.iota 16))
)
; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
(define-hardware
(name h-gr) (comment "general registers") (attrs PROFILE)
(type register WI (32))
(indices keyword ""
((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14)
(r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20)
(r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26)
(r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11)
(sp 1) (fp 2)))
)
(define-hardware
(name h-sr) (comment "special registers")
(type register WI (#x20000))
(get (index) (c-call SI "@arch@_h_sr_get_handler" index))
(set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval))
)
(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ())
(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ())
(dsh h-cbit "condition bit" () (register BI))
(dsh h-delay-insn "delay insn addr" () (register SI))
; Instruction operands.
(dnop sr "special register" (SEM-ONLY) h-sr f-nil)
(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil)
(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16)
(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16)
(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26)
(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26)
(dnop uimm-5 "imm5" () h-uint f-uimm5)
(dnop rD "destination register" () h-gr f-r1)
(dnop rA "source register A" () h-gr f-r2)
(dnop rB "source register B" () h-gr f-r3)
(dnop op-f-23 "f-op23" () h-uint f-op4)
(dnop op-f-3 "f-op3" () h-uint f-op5)
; For hi(foo).
(define-operand
(name hi16) (comment "high 16 bit immediate, sign optional")
(attrs SIGN-OPT)
(type h-hi16)
(index f-simm16)
(handlers (parse "hi16"))
)
; For lo(foo)
(define-operand
(name lo16) (comment "low 16 bit immediate, sign optional")
(attrs SIGN-OPT)
(type h-lo16)
(index f-lo16)
(handlers (parse "lo16"))
)
(define-operand
(name ui16nc)
(comment "16 bit immediate, sign optional")
(attrs)
(type h-lo16)
(index f-i16nc)
(handlers (parse "lo16"))
)
; Instructions.
; Branch releated instructions
(dni l-j "jump (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.j ${abs-26}"
(+ OP1_0 OP2_0 abs-26)
; We execute the delay slot before doin' the real branch
(delay 1 (set pc abs-26))
()
)
(dni l-jal "jump and link (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jal ${abs-26}"
(+ OP1_0 OP2_1 abs-26)
; We execute the delay slot before doin' the real branch
; Set LR to (delay insn addr + 4)
(sequence ()
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc abs-26)))
()
)
(dni l-jr "jump register (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jr $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16)
; We execute the delay slot before doin' the real branch
(delay 1 (set pc rA))
()
)
(dni l-jalr "jump register and link (absolute iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.jalr $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16)
; We save the value of rA in a temporary slot before setting
; the link register. This because "l.jalr r11" would cause
; a forever-and-ever loop otherwise.
;
; We execute the delay slot before doin' the real branch
(sequence ((WI tmp-slot))
(set tmp-slot rA)
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc tmp-slot)))
()
)
(dni l-bal "branch and link (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bal ${disp-26}"
(+ OP1_0 OP2_2 disp-26)
; We execute the delay slot before doin' the real branch
; Set LR to (delay insn addr + 4)
(sequence ()
(set (reg h-gr 11) (add (reg h-delay-insn) 4))
(delay 1 (set pc disp-26)))
()
)
(dni l-bnf "branch if condition bit not set (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bnf ${disp-26}"
(+ OP1_0 OP2_3 disp-26)
; We execute the delay slot before doin' the real branch
(if (eq cbit 0)
(sequence ()
(delay 1 (set pc disp-26))))
()
)
(dni l-bf "branch if condition bit is set (pc relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.bf ${disp-26}"
(+ OP1_0 OP2_4 disp-26)
; We execute the delay slot before doin' the real branch
(if (eq cbit 1)
(sequence ()
(delay 1 (set pc disp-26))))
()
)
(dni l-brk "break (exception)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.brk ${uimm-16}"
(+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16)
; FIXME should we do it like this ??
(c-call VOID "@cpu@_cpu_brk" uimm-16)
()
)
(dni l-rfe "return from exception"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.rfe $rA"
(+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16)
(sequence ()
(delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA))))
()
)
(dni l-sys "syscall (exception)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.sys ${uimm-16}"
(+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16)
(sequence()
(delay 1 (set pc (c-call SI "@cpu@_except" pc
#xc00 uimm-16))))
()
)
; Misc instructions
(dni l-nop "nop"
()
"l.nop"
(+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16)
(nop)
()
)
(dnmi l-ret "ret" ()
"l.ret"
(emit l-jr (rA 11) (uimm-16 0))
)
(dni l-movhi "movhi"
(DELAY-SLOT)
"l.movhi $rD,$hi16"
(+ OP1_0 OP2_6 hi16 rD rA)
(set rD (sll WI hi16 (const 16)))
()
)
; System releated instructions
(dni l-mfsr "mfsr"
(DELAY-SLOT)
"l.mfsr $rD,$rA"
(+ OP1_0 OP2_7 rD rA uimm-16)
(set rD (c-call SI "@cpu@_cpu_mfsr" rA))
()
)
(dni l-mtsr "mtsr"
(DELAY-SLOT)
"l.mtsr $rA,$rB"
(+ OP1_1 OP2_0 rA rB rD (f-i16-1 0))
(c-call VOID "@cpu@_cpu_mtsr" rA rB)
()
)
; Load instructions
(dni l-lw "load word"
(DELAY-SLOT)
"l.lw $rD,${simm-16}($rA)"
(+ OP1_2 OP2_0 rD rA simm-16)
(set rD (mem SI (add rA simm-16)))
()
)
(dni l-lbz "load byte (zero extend)"
(DELAY-SLOT)
"l.lbz $rD,${simm-16}($rA)"
(+ OP1_2 OP2_1 rD rA simm-16)
(set rD (zext SI (mem QI (add rA simm-16))))
()
)
(dni l-lbs "load byte (sign extend)"
(DELAY-SLOT)
"l.lbs $rD,${simm-16}($rA)"
(+ OP1_2 OP2_2 rD rA simm-16)
(set rD (ext SI (mem QI (add rA simm-16))))
()
)
(dni l-lhz "load halfword (zero extend)"
(DELAY-SLOT)
"l.lhz $rD,${simm-16}($rA)"
(+ OP1_2 OP2_3 rD simm-16 rA)
(set rD (zext SI (mem HI (add rA simm-16))))
()
)
(dni l-lhs "load halfword (sign extend)"
(DELAY-SLOT)
"l.lhs $rD,${simm-16}($rA)"
(+ OP1_2 OP2_4 rD rA simm-16)
(set rD (ext SI (mem HI (add rA simm-16))))
()
)
; Store instructions
;
; We have to use a multi field since the integer is splited over 2 fields
(define-pmacro (store-insn mnemonic op2-op mode-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " imm(reg)/reg")
(DELAY-SLOT)
(.str "l." mnemonic " ${ui16nc}($rA),$rB")
(+ OP1_3 op2-op rB rD ui16nc)
(set (mem mode-op (add rA ui16nc)) rB)
()
)
)
)
(store-insn sw OP2_5 SI)
(store-insn sb OP2_6 QI)
(store-insn sh OP2_7 HI)
; Shift and rotate instructions
; Reserved fields.
(dnf f-f-15-8 "nop" (RESERVED) 15 8)
(dnf f-f-10-3 "nop" (RESERVED) 10 3)
(dnf f-f-4-1 "nop" (RESERVED) 4 1)
(dnf f-f-7-3 "nop" (RESERVED) 7 3)
(define-pmacro (shift-insn mnemonic op4-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/imm")
()
(.str "l." mnemonic "i $rD,$rA,${uimm-5}")
(+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5)
(set rD (mnemonic rA uimm-5))
()
)
)
)
(shift-insn sll OP6_0)
(shift-insn srl OP6_1)
(shift-insn sra OP6_2)
(shift-insn ror OP6_4)
; Arethmetic insns
; Reserved fields.
(dnf f-f-10-7 "nop" (RESERVED) 10 7)
(define-pmacro (ar-insn-u mnemonic op2-op op5-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/lo16")
()
(.str "l." mnemonic "i $rD,$rA,$lo16")
(+ OP1_2 op2-op rD rA lo16)
(set rD (mnemonic rA (and lo16 #xffff)))
()
)
)
)
(define-pmacro (ar-insn-s mnemonic op2-op op5-op)
(begin
(dni (.sym l- mnemonic)
(.str "l." mnemonic " reg/reg/reg")
()
(.str "l." mnemonic " $rD,$rA,$rB")
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op)
(set rD (mnemonic rA rB))
()
)
(dni (.sym l- mnemonic "i")
(.str "l." mnemonic " reg/reg/lo16")
()
(.str "l." mnemonic "i $rD,$rA,$lo16")
(+ OP1_2 op2-op rD rA lo16)
(set rD (mnemonic rA lo16))
()
)
)
)
(ar-insn-s add OP2_5 OP7_0)
;;(ar-op-s addc OP2_5 OP7_0)
(ar-insn-s sub OP2_7 OP7_2)
(ar-insn-u and OP2_8 OP7_3)
(ar-insn-u or OP2_9 OP7_4)
(ar-insn-u xor OP2_10 OP7_5)
(ar-insn-u mul OP2_11 OP7_6)
;;(ar-op-u mac OP2_12 OP7_7)
(dni l-div "divide (signed)"
(DELAY-SLOT)
"l.div $rD,$rA,$rB"
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9)
(if VOID (eq rB (const 0))
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
(set rD (div rA rB)))
()
)
(dni l-divu "divide (unsigned)"
(DELAY-SLOT)
"l.divu $rD,$rA,$rB"
(+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10)
(if VOID (eq rB (const 0))
(c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL))
(set rD (udiv rA rB)))
()
)
; Compare instructions
; Reserved fields.
(dnf f-f-10-11 "nop" (RESERVED) 10 11)
; Register compare (both signed and unsigned)
(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op)
(begin
(dni (.sym l- "sf" (.sym sem-op "s"))
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "s $rA,$rB")
(+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
(dni (.sym l- "sf" (.sym sem-op "u"))
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "u $rA,$rB")
(+ op1-op op2-op op3-op rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
)
)
; Immediate compare (both signed and unsigned)
(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op)
(begin
(dni (.sym l- "sf" (.sym sem-op "si"))
(.str "l." mnemonic "si reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "si $rA,${simm-16}")
(+ op1-op op2-op op3-op-2 rA simm-16)
(set cbit (sem-op rA simm-16))
()
)
(dni (.sym l- "sf" (.sym sem-op "ui"))
(.str "l." mnemonic "ui reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}")
(+ op1-op op2-op op3-op rA uimm-16)
(set cbit (sem-op rA uimm-16))
()
)
)
)
(define-pmacro (sf-insn op5-op sem-op)
(begin
(dni (.sym l- "sf" sem-op)
(.str "l." mnemonic " reg/reg")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) " $rA,$rB")
(+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0))
(set cbit (sem-op rA rB))
()
)
(dni (.sym l- "sf" (.sym sem-op "i"))
(.str "l." mnemonic "i reg/imm")
(DELAY-SLOT)
(.str "l.sf" (.str sem-op) "i $rA,${simm-16}")
(+ OP1_2 OP2_14 op5-op rA simm-16)
(set cbit (sem-op rA simm-16))
()
)
)
)
(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt)
(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge)
(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt)
(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le)
(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt)
(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge)
(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt)
(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le)
(sf-insn OP5_0 eq)
(sf-insn OP5_1 ne)

164
cpu/openrisc.opc
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@@ -1,164 +0,0 @@
/* OpenRISC opcode support. -*- C -*-
Copyright 2000, 2001, 2003, 2005, 2011 Free Software Foundation, Inc.
Contributed by Red Hat Inc;
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file is an addendum to or32.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 64
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
extern long openrisc_sign_extend_16bit (long);
/* -- */
/* -- opc.c */
/* -- */
/* -- asm.c */
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
long
openrisc_sign_extend_16bit (long value)
{
return ((value & 0xffff) ^ 0x8000) - 0x8000;
}
/* Handle hi(). */
static const char *
parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "hi(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value >>= 16;
ret = value;
}
else
{
if (**strp == '-')
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
else
{
unsigned long value;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
ret = value;
}
}
*valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
/* Handle lo(). */
static const char *
parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "lo(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
}
else
{
if (**strp == '-')
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
else
{
unsigned long value;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
ret = value;
}
}
*valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
/* -- */
/* -- ibd.h */
extern long openrisc_sign_extend_16bit (long);
/* -- */

131
cpu/or1k.cpu Normal file
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@@ -0,0 +1,131 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
; Modified by Peter Gavin, pgavin@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
(include "simplify.inc")
; The OpenRISC family is a set of RISC microprocessor architectures with an
; emphasis on scalability and is targetted at embedded use.
; The CPU RTL development is a collaborative open source effort.
; http://opencores.org/or1k
; http://openrisc.net
(define-arch
(name or1k)
(comment "OpenRISC 1000")
(default-alignment aligned)
(insn-lsb0? #t)
(machs or32 or32nd or64 or64nd)
(isas openrisc)
)
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name openrisc)
; Base insturction length. The insns are always 32 bits wide.
(base-insn-bitsize 32)
)
(define-pmacro OR32-MACHS or32,or32nd)
(define-pmacro OR64-MACHS or64,or64nd)
(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
(define-pmacro ORFPX64-MACHS or64,or64nd)
(define-attr
(for model)
(type boolean)
(name NO-DELAY-SLOT)
(comment "does not have delay slots")
)
(if (keep-mach? (or32 or32nd))
(begin
(define-cpu
(name or1k32bf)
(comment "OpenRISC 1000 32-bit CPU family")
(insn-endian big)
(data-endian big)
(word-bitsize 32)
(file-transform "")
)
(define-mach
(name or32)
(comment "Generic OpenRISC 1000 32-bit CPU")
(cpu or1k32bf)
(bfd-name "or1k")
)
(define-mach
(name or32nd)
(comment "Generic OpenRISC 1000 32-bit CPU")
(cpu or1k32bf)
(bfd-name "or1knd")
)
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
(name or1200) (comment "OpenRISC 1200 model")
(attrs)
(mach or32)
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
; OpenRISC 1200 - 32-bit or1k CPU implementation
(define-model
(name or1200nd) (comment "OpenRISC 1200 model")
(attrs NO-DELAY-SLOT)
(mach or32nd)
(unit u-exec "Execution Unit" () 1 1 () () () ())
)
)
)
(if (keep-mach? (or64 or64nd))
(begin
(define-cpu
(name or1k64bf)
(comment "OpenRISC 1000 64-bit CPU family")
(insn-endian big)
(data-endian big)
(word-bitsize 64)
(file-transform "64")
)
(define-mach
(name or64)
(comment "Generic OpenRISC 1000 64-bit CPU")
(cpu or1k64bf)
(bfd-name "or1k64")
)
(define-mach
(name or64nd)
(comment "Generic OpenRISC 1000 ND 64-bit CPU")
(cpu or1k64bf)
(bfd-name "or1k64nd")
)
)
)
(include "or1kcommon.cpu")
(include "or1korbis.cpu")
(include "or1korfpx.cpu")

421
cpu/or1k.opc Normal file
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@@ -0,0 +1,421 @@
/* OpenRISC 1000 opcode support. -*- C -*-
Copyright 2000-2014 Free Software Foundation, Inc.
Originally ontributed for OR32 by Red Hat Inc;
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* This file is an addendum to or1k.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
/* -- */
/* -- opc.c */
/* -- */
/* -- asm.c */
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
static const char *
parse_disp26 (CGEN_CPU_DESC cd,
const char ** strp,
int opindex,
int opinfo,
enum cgen_parse_operand_result * resultp,
bfd_vma * valuep)
{
const char *errmsg = NULL;
enum cgen_parse_operand_result result_type;
if (strncasecmp (*strp, "plt(", 4) == 0)
{
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_PLT26,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 2) & 0xffff;
*valuep = value;
return errmsg;
}
return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep);
}
static const char *
parse_simm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "hi(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
& result_type, & value);
if (**strp != ')')
errmsg = MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
ret >>= 16;
ret &= 0xffff;
ret = (ret ^ 0x8000) - 0x8000;
}
}
else if (strncasecmp (*strp, "lo(", 3) == 0)
{
bfd_vma value;
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
ret &= 0xffff;
ret = (ret ^ 0x8000) - 0x8000;
}
}
else if (strncasecmp (*strp, "got(", 4) == 0)
{
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_GOT16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotpchi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTPC_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotpclo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTPC_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotoffhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTOFF_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gotofflo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_GOTOFF_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsgdhi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_GD_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsgdlo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_GD_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsldmhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDM_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tlsldmlo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDM_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "dtpoffhi(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDO_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "dtpofflo(", 9) == 0)
{
bfd_vma value;
*strp += 9;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LDO_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gottpoffhi(", 11) == 0)
{
bfd_vma value;
*strp += 11;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_IE_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "gottpofflo(", 11) == 0)
{
bfd_vma value;
*strp += 11;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_IE_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tpoffhi(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LE_HI16,
& result_type, & value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value >> 16) & 0xffff;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "tpofflo(", 8) == 0)
{
bfd_vma value;
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex,
BFD_RELOC_OR1K_TLS_LE_LO16,
&result_type, &value);
if (**strp != ')')
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
else
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
ret = value;
}
if (errmsg == NULL)
*valuep = ret;
return errmsg;
}
static const char *
parse_uimm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep)
{
const char *errmsg = parse_simm16(cd, strp, opindex, (long *) valuep);
if (errmsg == NULL)
*valuep &= 0xffff;
return errmsg;
}
/* -- */
/* -- ibd.h */
/* -- */

360
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; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.
(define-hardware
(name h-pc)
(comment "program counter")
(attrs PC (MACH ORBIS-MACHS))
(type pc UWI)
)
(define-pmacro REG-INDICES
((r0 0)
(r1 1)
(r2 2)
(r3 3)
(r4 4)
(r5 5)
(r6 6)
(r7 7)
(r8 8)
(r9 9)
(r10 10)
(r11 11)
(r12 12)
(r13 13)
(r14 14)
(r15 15)
(r16 16)
(r17 17)
(r18 18)
(r19 19)
(r20 20)
(r21 21)
(r22 22)
(r23 23)
(r24 24)
(r25 25)
(r26 26)
(r27 27)
(r28 28)
(r29 29)
(r30 30)
(r31 31)
(lr 9)
(sp 1)
(fp 2))
)
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
(attrs VIRTUAL (MACH ORFPX32-MACHS))
(type register SF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
(define-hardware
(name h-fdr) (comment "floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
(get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
(define-hardware
(name h-spr) (comment "special purpose registers")
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI (#x20000))
(get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
(set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
)
(define-pmacro spr-shift 11)
(define-pmacro (spr-address spr-group spr-index)
(or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
(enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
(define-hardware
(name h-gpr) (comment "general registers")
(attrs (MACH ORBIS-MACHS))
(type register UWI (32))
(indices keyword "" REG-INDICES)
(get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
(set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
)
(define-normal-enum
except-number
"Exception numbers"
()
EXCEPT-
(("NONE" #x00)
("RESET" #x01)
("BUSERR" #x02)
("DPF" #x03)
("IPF" #x04)
("TICK" #x05)
("ALIGN" #x06)
("ILLEGAL" #x07)
("INT" #x08)
("DTLBMISS" #x09)
("ITLBMISS" #x0a)
("RANGE" #x0b)
("SYSCALL" #x0c)
("FPE" #x0d)
("TRAP" #x0e)
)
)
(define-pmacro (raise-exception exnum)
(c-call VOID "@cpu@_exception" pc exnum))
(define-normal-enum
spr-groups
"special purpose register groups"
()
SPR-GROUP-
(("SYS" #x0)
("DMMU" #x1)
("IMMU" #x2)
("DCACHE" #x3)
("ICACHE" #x4)
("MAC" #x5)
("DEBUG" #x6)
("PERF" #x7)
("POWER" #x8)
("PIC" #x9)
("TICK" #xa)
("FPU" #xb)
)
)
(define-pmacro (spr-reg-info)
(.splice
(SYS VR #x000 "version register")
(SYS UPR #x001 "unit present register")
(SYS CPUCFGR #x002 "cpu configuration register")
(SYS DMMUCFGR #x003 "Data MMU configuration register")
(SYS IMMUCFGR #x004 "Insn MMU configuration register")
(SYS DCCFGR #x005 "Data cache configuration register")
(SYS ICCFGR #x006 "Insn cache configuration register")
(SYS DCFGR #x007 "Debug configuration register")
(SYS PCCFGR #x008 "Performance counters configuration register")
(SYS NPC #x010 "Next program counter")
(SYS SR #x011 "Supervision Regsiter")
(SYS PPC #x012 "Previous program counter")
(SYS FPCSR #x014 "Floating point control status register")
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n)))
(.iota #x10)))
(.unsplice
(.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n)))
(.iota #x200)))
(MAC MACLO #x001 "Multiply and accumulate result (low)")
(MAC MACHI #x002 "Multiply and accumulate result (high)")
(TICK TTMR #x000 "Tick timer mode register")
)
)
(define-normal-enum
spr-reg-indices
"special purpose register indicies"
()
SPR-INDEX-
(.map (.pmacro (args)
(.apply (.pmacro (group index n comment)
((.sym group "-" index) n))
args)
)
(spr-reg-info)
)
)
(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment)
(define-hardware
(name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index)))
(comment spr-comment)
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI)
(get () (reg UWI h-spr (spr-address spr-group spr-index)))
(set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval))
)
)
(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info))))
(define-pmacro (spr-field-info)
((SYS VR REV 5 0 "revision field")
(SYS VR CFG 23 16 "configuration template field")
(SYS VR VER 31 24 "version field")
(SYS UPR UP 0 0 "UPR present bit")
(SYS UPR DCP 1 1 "data cache present bit")
(SYS UPR ICP 2 2 "insn cache present bit")
(SYS UPR DMP 3 3 "data MMU present bit")
(SYS UPR MP 4 4 "MAC unit present bit")
(SYS UPR IMP 5 5 "insn MMU present bit")
(SYS UPR DUP 6 6 "debug unit present bit")
(SYS UPR PCUP 7 7 "performance counters unit present bit")
(SYS UPR PICP 8 8 "programmable interrupt controller present bit")
(SYS UPR PMP 9 9 "power management present bit")
(SYS UPR TTP 10 10 "tick timer present bit")
(SYS UPR CUP 31 24 "custom units present field")
(SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field")
(SYS CPUCFGR CGF 4 4 "custom GPR file bit")
(SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit")
(SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit")
(SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit")
(SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit")
(SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit")
(SYS CPUCFGR ND 10 10 "no transfer delay bit")
(SYS SR SM 0 0 "supervisor mode bit")
(SYS SR TEE 1 1 "tick timer exception enabled bit")
(SYS SR IEE 2 2 "interrupt exception enabled bit")
(SYS SR DCE 3 3 "data cache enabled bit")
(SYS SR ICE 4 4 "insn cache enabled bit")
(SYS SR DME 5 5 "data MMU enabled bit")
(SYS SR IME 6 6 "insn MMU enabled bit")
(SYS SR LEE 7 7 "little endian enabled bit")
(SYS SR CE 8 8 "CID enable bit")
(SYS SR F 9 9 "flag bit")
(SYS SR CY 10 10 "carry bit")
(SYS SR OV 11 11 "overflow bit")
(SYS SR OVE 12 12 "overflow exception enabled bit")
(SYS SR DSX 13 13 "delay slot exception bit")
(SYS SR EPH 14 14 "exception prefix high bit")
(SYS SR FO 15 15 "fixed one bit")
(SYS SR SUMRA 16 16 "SPRs user mode read access bit")
(SYS SR CID 31 28 "context ID field")
(SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit")
(SYS FPCSR RM 2 1 "floating point rounding mode field")
(SYS FPCSR OVF 3 3 "floating point overflow flag bit")
(SYS FPCSR UNF 4 4 "floating point underflow bit")
(SYS FPCSR SNF 5 5 "floating point SNAN flag bit")
(SYS FPCSR QNF 6 6 "floating point QNAN flag bit")
(SYS FPCSR ZF 7 7 "floating point zero flag bit")
(SYS FPCSR IXF 8 8 "floating point inexact flag bit")
(SYS FPCSR IVF 9 9 "floating point invalid flag bit")
(SYS FPCSR INF 10 10 "floating point infinity flag bit")
(SYS FPCSR DZF 11 11 "floating point divide by zero flag bit")
)
)
(define-normal-enum
spr-field-msbs
"SPR field msb positions"
()
SPR-FIELD-MSB-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
((.sym group "-" index "-" field) msb)
)
args
)
)
(spr-field-info)
)
)
(define-normal-enum
spr-field-lsbs
"SPR field lsb positions"
()
SPR-FIELD-SIZE-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
((.sym group "-" index "-" field) lsb)
)
args
)
)
(spr-field-info)
)
)
(define-normal-enum
spr-field-masks
"SPR field masks"
()
SPR-FIELD-MASK-
(.map (.pmacro (args)
(.apply (.pmacro (group index field msb lsb comment)
(.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb))
)
args
)
)
(spr-field-info)
)
)
(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment)
(.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field)))
)
(begin
(define-hardware
(name spr-field-name)
(comment spr-field-comment)
(attrs VIRTUAL (MACH ORBIS-MACHS))
(type register UWI)
(get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb))
(set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value))
)
)
)
)
(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info))))
(define-attr
(type boolean)
(for insn)
(name DELAYED-CTI)
(comment "delayed control transfer instruction")
(values #f #t)
(default #f)
)
(define-attr
(for insn)
(type boolean)
(name NOT-IN-DELAY-SLOT)
(comment "instruction cannot be in delay slot")
(values #f #t)
(default #f)
)
(define-attr
(for insn)
(type boolean)
(name FORCED-CTI)
(comment "instruction may forcefully transfer control (e.g., rfe)")
)

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; OpenRISC 1000 architecture. -*- Scheme -*-
; Copyright 2000-2014 Free Software Foundation, Inc.
; Contributed by Peter Gavin, pgavin@gmail.com
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, see <http://www.gnu.org/licenses/>
; Initial ORFPX32 instruction set
; I'm not sure how CGEN handles rounding in FP operations, except for
; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and
; lf.div do not round according to the FPCSR RM field.
; NaN, overflow, and underflow are not yet handled either.
(define-normal-insn-enum insn-opcode-float-regreg
"floating point reg/reg insn opcode enums" ()
OPC_FLOAT_REGREG_ f-op-7-8
(("ADD_S" #x00)
("SUB_S" #x01)
("MUL_S" #x02)
("DIV_S" #x03)
("ITOF_S" #x04)
("FTOI_S" #x05)
("REM_S" #x06)
("MADD_S" #x07)
("SFEQ_S" #x08)
("SFNE_S" #x09)
("SFGT_S" #x0a)
("SFGE_S" #x0b)
("SFLT_S" #x0c)
("SFLE_S" #x0d)
("ADD_D" #x10)
("SUB_D" #x11)
("MUL_D" #x12)
("DIV_D" #x13)
("ITOF_D" #x14)
("FTOI_D" #x15)
("REM_D" #x16)
("MADD_D" #x17)
("SFEQ_D" #x18)
("SFNE_D" #x19)
("SFGT_D" #x1a)
("SFGE_D" #x1b)
("SFLT_D" #x1c)
("SFLE_D" #x1d)
("CUST1_S" #xd0)
("CUST1_D" #xe0)
)
)
(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(define-pmacro (float-regreg-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf." mnemonic ".s reg/reg/reg")
((MACH ORFPX-MACHS))
(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
(set SF rDSF (mnemonic SF rASF rBSF))
()
)
(dni (.sym lf- mnemonic -d)
(.str "lf." mnemonic ".d reg/reg/reg")
((MACH ORFPX64-MACHS))
(.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
(set DF rDDF (mnemonic DF rADF rBDF))
()
)
)
)
(float-regreg-insn add)
(float-regreg-insn sub)
(float-regreg-insn mul)
(float-regreg-insn div)
(dni lf-rem-s
"lf.rem.s reg/reg/reg"
((MACH ORFPX-MACHS))
"lf.rem.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
(set SF rDSF (rem SF rASF rBSF))
()
)
(dni lf-rem-d
"lf.rem.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.rem.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
(set DF rDDF (mod DF rADF rBDF))
()
)
(define-pmacro (get-rounding-mode)
(case INT sys-fpcsr-rm
((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
((1) 3) ; TOWARD-ZERO
((2) 4) ; TOWARD-POSITIVE
(else 5) ; TOWARD-NEGATIVE
)
)
(dni lf-itof-s
"lf.itof.s reg/reg"
((MACH ORFPX-MACHS))
"lf.itof.s $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
()
)
(dni lf-itof-d
"lf.itof.d reg/reg"
((MACH ORFPX64-MACHS))
"lf.itof.d $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
(set DF rDDF (float DF (get-rounding-mode) rA))
()
)
(dni lf-ftoi-s
"lf.ftoi.s reg/reg"
((MACH ORFPX-MACHS))
"lf.ftoi.s $rD,$rASF"
(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
()
)
(dni lf-ftoi-d
"lf.ftoi.d reg/reg"
((MACH ORFPX64-MACHS))
"lf.ftoi.d $rD,$rADF"
(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
(set DI rD (fix DI (get-rounding-mode) rADF))
()
)
(define-pmacro (float-setflag-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
((MACH ORFPX-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
(set BI sys-sr-f (mnemonic SF rASF rBSF))
()
)
(dni (.sym lf- mnemonic -d)
(.str "lf.sf" mnemonic ".d reg/reg")
((MACH ORFPX64-MACHS))
(.str "lf.sf" mnemonic ".d $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
(set BI sys-sr-f (mnemonic DF rADF rBDF))
()
)
)
)
(float-setflag-insn eq)
(float-setflag-insn ne)
(float-setflag-insn ge)
(float-setflag-insn gt)
(float-setflag-insn lt)
(float-setflag-insn le)
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
((MACH ORFPX-MACHS))
"lf.madd.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
()
)
(dni lf-madd-d
"lf.madd.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.madd.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
(set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
()
)
(define-pmacro (float-cust-insn cust-num)
(begin
(dni (.sym "lf-cust" cust-num "-s")
(.str "lf.cust" cust-num ".s")
((MACH ORFPX-MACHS))
(.str "lf.cust" cust-num ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
(nop)
()
)
(dni (.sym "lf-cust" cust-num "-d")
(.str "lf.cust" cust-num ".d")
((MACH ORFPX64-MACHS))
(.str "lf.cust" cust-num ".d")
(+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
(nop)
()
)
)
)
(float-cust-insn "1")