forked from Imagelibrary/binutils-gdb
opcodes:
* arm-opc.h: Delete; fold contents into ... * arm-dis.c: ... here. Move includes of internal COFF headers next to includes of internal ELF headers. (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused. (struct arm_opcode): Rename struct opcode32. Make 'assembler' const. (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const. (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames) (iwmmxt_wwnames, iwmmxt_wwssnames): Make const. (regnames): Remove iWMMXt coprocessor register sets. (iwmmxt_regnames, iwmmxt_cregnames): New statics. (get_arm_regnames): Adjust fourth argument to match above changes. (set_iwmmxt_regnames): Delete. (print_insn_arm): Constify 'c'. Use ISO syntax for function pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames and iwmmxt_cregnames, not set_iwmmxt_regnames. (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use ISO syntax for function pointer calls. include: * dis-asm.h (get_arm_regnames): Update prototype.
This commit is contained in:
Zack Weinberg
@@ -24,21 +24,17 @@
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#include "dis-asm.h"
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#include "opcode/arm.h"
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#include "arm-opc.h"
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#include "coff/internal.h"
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#include "libcoff.h"
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#include "opintl.h"
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#include "safe-ctype.h"
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/* FIXME: This shouldn't be done here. */
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#include "coff/internal.h"
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#include "libcoff.h"
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#include "elf-bfd.h"
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#include "elf/internal.h"
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#include "elf/arm.h"
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#ifndef streq
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#endif
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/* FIXME: Belongs in global header. */
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#ifndef strneq
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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@@ -47,7 +43,19 @@
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#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
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#endif
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#define WORD_ADDRESS(pc) ((pc) & ~0x3)
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struct opcode32
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{
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unsigned long arch; /* Architecture defining this insn. */
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unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
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const char *assembler; /* How to disassemble this insn. */
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};
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struct opcode16
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{
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unsigned long arch; /* Architecture defining this insn. */
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unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
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const char *assembler; /* How to disassemble this insn. */
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};
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/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
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ordered: they must be searched linearly from the top to obtain a correct
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@@ -101,7 +109,7 @@
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%E print the LSB and WIDTH fields of a BFI or BFC instruction.
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%V print the 16-bit immediate field of a MOVT or MOVW instruction. */
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static const struct arm_opcode arm_opcodes[] =
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static const struct opcode32 arm_opcodes[] =
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{
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/* ARM instructions. */
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{ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
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@@ -644,7 +652,7 @@ static const struct arm_opcode arm_opcodes[] =
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%<bitnum>'c print specified char iff bit is one
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%<bitnum>?ab print a if bit is one else print b. */
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static const struct thumb_opcode thumb_opcodes[] =
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static const struct opcode16 thumb_opcodes[] =
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{
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/* Thumb instructions. */
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@@ -812,7 +820,7 @@ static const struct thumb_opcode thumb_opcodes[] =
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is guaranteed never to catch a special-case bit pattern with a more
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general mask, which is important, because this instruction encoding
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makes heavy use of special-case bit patterns. */
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static const struct arm_opcode thumb32_opcodes[] =
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static const struct opcode32 thumb32_opcodes[] =
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{
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/* Instructions defined in the basic V6T2 set. */
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{ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"},
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@@ -1018,20 +1026,25 @@ static const struct arm_opcode thumb32_opcodes[] =
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{0, 0, 0, 0}
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};
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static char * arm_conditional[] =
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static const char *const arm_conditional[] =
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{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "<und>"};
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static const char *const arm_fp_const[] =
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{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
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static const char *const arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
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typedef struct
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{
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const char * name;
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const char * description;
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const char * reg_names[16];
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const char *name;
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const char *description;
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const char *reg_names[16];
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}
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arm_regname;
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static arm_regname regnames[] =
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static const arm_regname regnames[] =
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{
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{ "raw" , "Select raw register names",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
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@@ -1045,22 +1058,28 @@ static arm_regname regnames[] =
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
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{ "special-atpcs", "Select special register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
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{ "iwmmxt_regnames", "Select register names used on the Intel Wireless MMX technology coprocessor",
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{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}},
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{ "iwmmxt_Cregnames", "Select control register names used on the Intel Wireless MMX technology coprocessor",
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{"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}}
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};
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static char * iwmmxt_wwnames[] =
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static const char *const iwmmxt_wwnames[] =
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{"b", "h", "w", "d"};
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static char * iwmmxt_wwssnames[] =
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static const char *const iwmmxt_wwssnames[] =
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{"b", "bus", "b", "bss",
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"h", "hus", "h", "hss",
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"w", "wus", "w", "wss",
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"d", "dus", "d", "dss"
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};
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static const char *const iwmmxt_regnames[] =
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{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
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"wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
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};
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static const char *const iwmmxt_cregnames[] =
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{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
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"wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
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};
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/* Default to GCC register name set. */
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static unsigned int regname_selected = 1;
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@@ -1069,11 +1088,6 @@ static unsigned int regname_selected = 1;
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static bfd_boolean force_thumb = FALSE;
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static char * arm_fp_const[] =
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{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
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static char * arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
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/* Functions. */
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int
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@@ -1092,7 +1106,7 @@ set_arm_regname_option (int option)
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int
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get_arm_regnames (int option, const char **setname, const char **setdescription,
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const char ***register_names)
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const char *const **register_names)
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{
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*setname = regnames[option].name;
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*setdescription = regnames[option].description;
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@@ -1131,33 +1145,14 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream)
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}
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}
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static int
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set_iwmmxt_regnames (void)
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{
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const char * setname;
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const char * setdesc;
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const char ** regnames;
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int iwmmxt_regnames = 0;
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int num_regnames = get_arm_regname_num_options ();
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get_arm_regnames (iwmmxt_regnames, &setname,
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&setdesc, ®names);
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while ((strcmp ("iwmmxt_regnames", setname))
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&& (iwmmxt_regnames < num_regnames))
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get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, ®names);
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return iwmmxt_regnames;
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}
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/* Print one ARM instruction from PC on INFO->STREAM. */
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static void
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print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct arm_opcode *insn;
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const struct opcode32 *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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static int iwmmxt_regnames = 0;
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fprintf_ftype func = info->fprintf_func;
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for (insn = arm_opcodes; insn->assembler; insn++)
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{
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@@ -1174,7 +1169,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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|| (insn->mask & 0xF0000000) == 0xF0000000
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|| (insn->mask == 0 && insn->value == 0)))
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{
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char * c;
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const char *c;
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for (c = insn->assembler; *c; c++)
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{
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@@ -1281,9 +1276,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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offset = -offset;
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func (stream, "[pc, #%d]\t; ", offset);
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(*info->print_address_func)
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(offset + pc + 8, info);
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info->print_address_func (offset + pc + 8, info);
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}
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else
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{
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@@ -1340,8 +1333,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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break;
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case 'b':
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(*info->print_address_func)
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(BDISP (given) * 4 + pc + 8, info);
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{
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int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
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info->print_address_func (disp*4 + pc + 8, info);
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}
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break;
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case 'c':
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@@ -1663,34 +1658,18 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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case 'g':
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{
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long reg;
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int current_regnames;
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if (! iwmmxt_regnames)
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iwmmxt_regnames = set_iwmmxt_regnames ();
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current_regnames = set_arm_regname_option
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(iwmmxt_regnames);
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", arm_regnames[reg]);
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set_arm_regname_option (current_regnames);
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func (stream, "%s", iwmmxt_regnames[reg]);
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}
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break;
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case 'G':
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{
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long reg;
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int current_regnames;
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if (! iwmmxt_regnames)
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iwmmxt_regnames = set_iwmmxt_regnames ();
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current_regnames = set_arm_regname_option
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(iwmmxt_regnames + 1);
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", arm_regnames[reg]);
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set_arm_regname_option (current_regnames);
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func (stream, "%s", iwmmxt_cregnames[reg]);
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}
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break;
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@@ -1901,14 +1880,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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static void
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print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct thumb_opcode *insn;
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const struct opcode16 *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = thumb_opcodes; insn->assembler; insn++)
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if ((given & insn->mask) == insn->value)
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{
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char * c = insn->assembler;
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const char *c = insn->assembler;
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for (; *c; c++)
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{
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int domaskpc = 0;
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@@ -2070,8 +2049,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
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case 'B':
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reg = ((reg ^ (1 << bitend)) - (1 << bitend));
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(*info->print_address_func)
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(reg * 2 + pc + 4, info);
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info->print_address_func (reg * 2 + pc + 4, info);
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break;
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case 'c':
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@@ -2127,14 +2105,14 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
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static void
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print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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const struct arm_opcode *insn;
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const struct opcode32 *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = thumb32_opcodes; insn->assembler; insn++)
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if ((given & insn->mask) == insn->value)
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{
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char * c = insn->assembler;
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const char *c = insn->assembler;
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for (; *c; c++)
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{
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if (*c != '%')
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