gas/

* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.
2013-11-05 20:50:18 +00:00
parent 4e50d5f863
commit 68a6428382
19 changed files with 158 additions and 37 deletions
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
+	(convert_from_csel): Likewise.
+	* aarch64-opc.c (operand_general_constraint_met_p): Handle
+	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
+	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
+	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
+	COND for cinc, cset, cinv, csetm and cneg.
+	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
+	* aarch64-asm-2.c: Re-generated.
+	* aarch64-dis-2.c: Ditto.
+	* aarch64-opc-2.c: Ditto.
+
 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>

 	* aarch64-opc.c (set_syntax_error): New function.
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -303,10 +303,10 @@ aarch64_insert_operand (const aarch64_operand *self,
    case 55:
    case 56:
    case 57:
-    case 65:
    case 66:
    case 67:
    case 68:
+    case 69:
      return aarch64_ins_imm (self, info, code, inst);
    case 37:
    case 38:
@@ -324,33 +324,34 @@ aarch64_insert_operand (const aarch64_operand *self,
    case 61:
      return aarch64_ins_fbits (self, info, code, inst);
    case 63:
+    case 64:
      return aarch64_ins_cond (self, info, code, inst);
-    case 69:
-    case 75:
-      return aarch64_ins_addr_simple (self, info, code, inst);
    case 70:
-      return aarch64_ins_addr_regoff (self, info, code, inst);
+    case 76:
+      return aarch64_ins_addr_simple (self, info, code, inst);
    case 71:
+      return aarch64_ins_addr_regoff (self, info, code, inst);
    case 72:
    case 73:
-      return aarch64_ins_addr_simm (self, info, code, inst);
    case 74:
+      return aarch64_ins_addr_simm (self, info, code, inst);
+    case 75:
      return aarch64_ins_addr_uimm12 (self, info, code, inst);
-    case 76:
-      return aarch64_ins_simd_addr_post (self, info, code, inst);
    case 77:
-      return aarch64_ins_sysreg (self, info, code, inst);
+      return aarch64_ins_simd_addr_post (self, info, code, inst);
    case 78:
-      return aarch64_ins_pstatefield (self, info, code, inst);
+      return aarch64_ins_sysreg (self, info, code, inst);
    case 79:
+      return aarch64_ins_pstatefield (self, info, code, inst);
    case 80:
    case 81:
    case 82:
-      return aarch64_ins_sysins_op (self, info, code, inst);
    case 83:
+      return aarch64_ins_sysins_op (self, info, code, inst);
    case 84:
-      return aarch64_ins_barrier (self, info, code, inst);
    case 85:
+      return aarch64_ins_barrier (self, info, code, inst);
+    case 86:
      return aarch64_ins_prfop (self, info, code, inst);
    default: assert (0); abort ();
    }
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -7690,11 +7690,11 @@ aarch64_extract_operand (const aarch64_operand *self,
    case 55:
    case 56:
    case 57:
-    case 64:
    case 65:
    case 66:
    case 67:
    case 68:
+    case 69:
      return aarch64_ext_imm (self, info, code, inst);
    case 37:
    case 38:
@@ -7714,33 +7714,34 @@ aarch64_extract_operand (const aarch64_operand *self,
    case 61:
      return aarch64_ext_fbits (self, info, code, inst);
    case 63:
+    case 64:
      return aarch64_ext_cond (self, info, code, inst);
-    case 69:
-    case 75:
-      return aarch64_ext_addr_simple (self, info, code, inst);
    case 70:
-      return aarch64_ext_addr_regoff (self, info, code, inst);
+    case 76:
+      return aarch64_ext_addr_simple (self, info, code, inst);
    case 71:
+      return aarch64_ext_addr_regoff (self, info, code, inst);
    case 72:
    case 73:
-      return aarch64_ext_addr_simm (self, info, code, inst);
    case 74:
+      return aarch64_ext_addr_simm (self, info, code, inst);
+    case 75:
      return aarch64_ext_addr_uimm12 (self, info, code, inst);
-    case 76:
-      return aarch64_ext_simd_addr_post (self, info, code, inst);
    case 77:
-      return aarch64_ext_sysreg (self, info, code, inst);
+      return aarch64_ext_simd_addr_post (self, info, code, inst);
    case 78:
-      return aarch64_ext_pstatefield (self, info, code, inst);
+      return aarch64_ext_sysreg (self, info, code, inst);
    case 79:
+      return aarch64_ext_pstatefield (self, info, code, inst);
    case 80:
    case 81:
    case 82:
-      return aarch64_ext_sysins_op (self, info, code, inst);
    case 83:
+      return aarch64_ext_sysins_op (self, info, code, inst);
    case 84:
-      return aarch64_ext_barrier (self, info, code, inst);
    case 85:
+      return aarch64_ext_barrier (self, info, code, inst);
+    case 86:
      return aarch64_ext_prfop (self, info, code, inst);
    default: assert (0); abort ();
    }
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1601,12 +1601,14 @@ convert_ubfm_to_lsl (aarch64_inst *inst)

 /* CINC <Wd>, <Wn>, <cond>
     is equivalent to:
-   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>).  */
+   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
+     where <cond> is not AL or NV.  */

 static int
 convert_from_csel (aarch64_inst *inst)
 {
-  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
    {
      copy_operand_info (inst, 2, 3);
      inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
@@ -1618,13 +1620,15 @@ convert_from_csel (aarch64_inst *inst)

 /* CSET <Wd>, <cond>
     is equivalent to:
-   CSINC <Wd>, WZR, WZR, invert(<cond>).  */
+   CSINC <Wd>, WZR, WZR, invert(<cond>)
+     where <cond> is not AL or NV.  */

 static int
 convert_csinc_to_cset (aarch64_inst *inst)
 {
  if (inst->operands[1].reg.regno == 0x1f
-      && inst->operands[2].reg.regno == 0x1f)
+      && inst->operands[2].reg.regno == 0x1f
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
    {
      copy_operand_info (inst, 1, 3);
      inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -87,7 +87,8 @@ const struct aarch64_operand aarch64_operands[] =
  {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
-  {AARCH64_OPND_CLASS_NIL, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+  {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+  {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1286,6 +1286,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	}
      break;

+    case AARCH64_OPND_CLASS_COND:
+      if (type == AARCH64_OPND_COND1
+	  && (opnds[idx].cond->value & 0xe) == 0xe)
+	{
+	  /* Not allow AL or NV.  */
+	  set_syntax_error (mismatch_detail, idx, NULL);
+	}
+      break;
+
    case AARCH64_OPND_CLASS_ADDRESS:
      /* Check writeback.  */
      switch (opcode->iclass)
@@ -2524,6 +2533,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
      break;

    case AARCH64_OPND_COND:
+    case AARCH64_OPND_COND1:
      snprintf (buf, size, "%s", opnd->cond->names[0]);
      break;

--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1782,13 +1782,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
  /* Conditional select.  */
  {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
  {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
-  {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+  {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
  {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
-  {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+  {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
  {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
  /* Crypto AES.  */
  {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
  {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
@@ -2235,7 +2235,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
    Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale),			\
      "the number of bits after the binary point in the fixed-point value")\
    X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate")		\
-    Y(NIL, cond, "COND", 0, F(), "a condition")				\
+    Y(COND, cond, "COND", 0, F(), "a condition")			\
+    Y(COND, cond, "COND1", 0, F(),					\
+      "one of the standard conditions, excluding AL and NV.")		\
    X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
      "21-bit PC-relative address of a 4KB page")			\
    Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2,	\