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RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]

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T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds the additional extension "XTheadVdot" based on the
"V" extension, and it provides four 8-bit multiply and add with
32-bit instructions for the "v" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([2]).

Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com>

[1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot
[2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add support
	for "XTheadVdot" extension.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi: Likewise.
	* testsuite/gas/riscv/march-help.l: Likewise.
	* testsuite/gas/riscv/x-thead-vdot.d: New test.
	* testsuite/gas/riscv/x-thead-vdot.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New.
	* opcode/riscv.h (enum riscv_insn_class): Add insn class for
	XTheadVdot.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
This commit is contained in:
Jin Ma
2025-03-17 14:07:35 +08:00
committed by Nelson Chu
parent e4c9f0e6c3
commit 66b81b40dc
8 changed files with 97 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
include/opcode/riscv-opc.h
View File

@@ -3699,6 +3699,21 @@
#define MASK_TH_VFMVFS 0xfe0ff07f
#define MATCH_TH_VFMVSF 0x36005057
#define MASK_TH_VFMVSF 0xfff0707f
/* Vendor-specific (T-Head) XTheadVdot instructions. */
#define MATCH_TH_VMAQA_VV 0x8000600b
#define MASK_TH_VMAQA_VV 0xfc00707f
#define MATCH_TH_VMAQA_VX 0x8400600b
#define MASK_TH_VMAQA_VX 0xfc00707f
#define MATCH_TH_VMAQAU_VV 0x8800600b
#define MASK_TH_VMAQAU_VV 0xfc00707f
#define MATCH_TH_VMAQAU_VX 0x8c00600b
#define MASK_TH_VMAQAU_VX 0xfc00707f
#define MATCH_TH_VMAQASU_VV 0x9000600b
#define MASK_TH_VMAQASU_VV 0xfc00707f
#define MATCH_TH_VMAQASU_VX 0x9400600b
#define MASK_TH_VMAQASU_VX 0xfc00707f
#define MATCH_TH_VMAQAUS_VX 0x9c00600b
#define MASK_TH_VMAQAUS_VX 0xfc00707f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f

1
include/opcode/riscv.h
View File

@@ -554,6 +554,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADMEMPAIR,
INSN_CLASS_XTHEADSYNC,
INSN_CLASS_XTHEADVECTOR,
INSN_CLASS_XTHEADVDOT,
INSN_CLASS_XTHEADZVAMO,
INSN_CLASS_XVENTANACONDOPS,
INSN_CLASS_XSFVCP,