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* mips-opc.c (MT32): New define.

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(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
bottom to avoid opcode collision with "mftr" and "mttr".
Add MT instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
This commit is contained in:
Chao-ying Fu
2005-09-06 18:46:57 +00:00
parent 3a4cf4826b
commit 61cc026711
3 changed files with 127 additions and 5 deletions
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56
opcodes/mips-dis.c
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@@ -376,7 +376,7 @@ const struct mips_arch_choice mips_arch_choices[] =
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP,
ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -771,6 +771,34 @@ print_insn_args (const char *d,
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
break;
case 't': /* Coprocessor 0 reg name */
(*info->fprintf_func) (info->stream, "%s",
mips_cp0_names[(l >> OP_SH_RT) &
OP_MASK_RT]);
break;
case 'T': /* Coprocessor 0 reg name */
{
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
/* CP0 register including 'sel' code for mftc0, to be
printed textually if known. If not known, print both
CP0 register name and sel numerically since CP0 register
with sel 0 may have a name unrelated to register being
printed. */
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
(*info->fprintf_func) (info->stream, "%s", n->name);
else
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
break;
}
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
@@ -841,6 +869,32 @@ print_insn_args (const char *d,
(*info->fprintf_func) (info->stream, "%d", delta);
break;
case '!':
(*info->fprintf_func) (info->stream, "%ld",
(l >> OP_SH_MT_U) & OP_MASK_MT_U);
break;
case '$':
(*info->fprintf_func) (info->stream, "%ld",
(l >> OP_SH_MT_H) & OP_MASK_MT_H);
break;
case '*':
(*info->fprintf_func) (info->stream, "$ac%ld",
(l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
break;
case '&':
(*info->fprintf_func) (info->stream, "$ac%ld",
(l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
break;
case 'g':
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
(*info->fprintf_func) (info->stream, "$%ld",
(l >> OP_SH_RD) & OP_MASK_RD);
break;
case 's':
case 'b':
case 'r':