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opcodes: blackfin: fix decoding of dsp mult insns

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When assigning to a register half, the mac0 part of the mult insn
was not decoding properly.  It would always show a full dreg instead
of the dreg low half.

Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2011-02-13 18:54:49 +00:00
parent 36f446111a
commit 4db6639409
8 changed files with 35 additions and 25 deletions
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4
opcodes/bfin-dis.c
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@@ -3084,7 +3084,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
if (w1)
{
OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
OUTS (outf, " = ");
decode_multfunc (h01, h11, src0, src1, outf);
@@ -3099,7 +3099,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
if (w0)
{
OUTS (outf, dregs (dst));
OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
OUTS (outf, " = ");
decode_multfunc (h00, h10, src0, src1, outf);
}