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import gdb-1999-11-16 snapshot

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This commit is contained in:
Jason Molenda
1999-11-17 02:31:06 +00:00
parent 2daf4fd896
commit 4ce44c668d
45 changed files with 1665 additions and 1200 deletions
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83
sim/d10v/ChangeLog
View File

@@ -1,7 +1,88 @@
Fri Oct 29 18:34:28 1999 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (move_to_cr): Don't allow user to set PSW.DM in either
DPSW and BPSW.
Thu Oct 28 01:26:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_5F20): Use SET_HW_PSW when updating PSW.
(PSW_HW_MASK): Declare.
* d10v_sim.h (move_to_cr): Add ``psw_hw_p'' parameter.
(SET_CREG, SET_PSW_BIT): Update.
(SET_HW_CREG, SET_HW_PSW): Define.
Sun Oct 24 21:38:04 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_d10v_translate_dmap_addr): Fix extraction of IOSP
for DMAP3.
Sun Oct 24 16:04:16 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_d10v_translate_addr): New function.
(xfer_mem): Rewrite. Use sim_d10v_translate_addr.
(map_memory): Make INLINE.
Sun Oct 24 13:45:19 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_d10v_translate_dmap_addr): New function.
(dmem_addr): Rewrite. Use sim_d10v_translate_dmap_addr. Change
offset parameter to type uint16.
* d10v_sim.h (dmem_addr): Update declaration.
Sun Oct 24 13:07:31 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (imap_register, set_imap_register, dmap_register,
set_imap_register): Use map_memory.
(DMAP): Update.
(sim_create_inferior): Initialize all DMAP registers. NOTE that
DMAP2, in internal memory mode, is set to 0x0000 and NOT
0x2000. This is consistent with the older d10v boards.
Sun Oct 24 11:22:12 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_d10v_translate_imap_addr): New function.
(imem_addr): Rewrite. Use sim_d10v_translate_imap_addr.
(last_from, last_to): Declare.
Sun Oct 24 01:21:56 1999 Andrew Cagney <cagney@b1.cygnus.com>
* d10v_sim.h (struct d10v_memory): Define. Support very long
memories.
(struct _state): Replace imem, dmem and umem by mem.
(IMAP_BLOCK_SIZE, DMAP_BLOCK_SIZE, SEGMENT_SIZE, IMEM_SEGMENTS,
DMEM_SEGMENTS, UMEM_SEGMENTS): Define.
* interp.c (map_memory): New function.
(sim_size, xfer_memory, imem_addr, dmem_addr): Update.
(UMEM_SEGMENTS): Moveed to "d10v_sim.h".
(IMEM_SIZEDMEM_SIZE): Delete.
Sat Oct 23 20:06:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c: Include "sim-d10v.h".
(imap_register, set_imap_register, dmap_register,
set_dmap_register, spi_register, spu_register, set_spi_register,
set_spu_register): New functions.
(sim_create_inferior): Update.
(sim_fetch_register, sim_store_register): Rewrite. Use enums
defined in sim-d10v.h.
* d10v_sim.h (DEBUG_MEMORY): Define.
(IMAP0, IMAP1, DMAP, SET_IMAP0, SET_IMAP1, SET_DMAP): Delete.
Sat Oct 23 18:41:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_open): Allow a debug value to be passed to the -t
option.
(lookup_hash): Don't exit on an illegal instruction.
(do_long, do_2_short, do_parallel): Check for failed instruction
lookup.
Mon Oct 18 18:03:24 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* simops.c (OP_3220): Fix trace output for illegal accumulator
message.
message.
1999-09-14 Nick Clifton <nickc@cygnus.com>

63
sim/d10v/d10v_sim.h
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@@ -13,6 +13,7 @@
#define DEBUG_MEMSIZE 0x00000008
#define DEBUG_INSTRUCTION 0x00000010
#define DEBUG_TRAP 0x00000020
#define DEBUG_MEMORY 0x00000040
#ifndef DEBUG
#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
@@ -197,6 +198,37 @@ enum {
} \
while (0)
/* d10v memory: There are three separate d10v memory regions IMEM,
UMEM and DMEM. The IMEM and DMEM are further broken down into
blocks (very like VM pages). */
enum
{
IMAP_BLOCK_SIZE = 0x20000,
DMAP_BLOCK_SIZE = 0x4000,
};
/* Implement the three memory regions using sparse arrays. Allocate
memory using ``segments''. A segment must be at least as large as
a BLOCK - ensures that an access that doesn't cross a block
boundary can't cross a segment boundary */
enum
{
SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
IMEM_SEGMENTS = 8, /* 1MB */
DMEM_SEGMENTS = 8, /* 1MB */
UMEM_SEGMENTS = 128 /* 16MB */
};
struct d10v_memory
{
uint8 *insn[IMEM_SEGMENTS];
uint8 *data[DMEM_SEGMENTS];
uint8 *unif[UMEM_SEGMENTS];
uint8 fault[16];
};
struct _state
{
reg_t regs[16]; /* general-purpose registers */
@@ -209,7 +241,8 @@ struct _state
reg_t cregs[16]; /* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL))
#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
@@ -232,10 +265,11 @@ struct _state
int exception;
int pc_changed;
/* NOTE: everything below this line is not reset by sim_create_inferior() */
uint8 *imem;
uint8 *dmem;
uint8 *umem[128];
/* NOTE: everything below this line is not reset by
sim_create_inferior() */
struct d10v_memory mem;
enum _ins_type ins_type;
} State;
@@ -283,7 +317,8 @@ enum
#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0)
#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0, 1)
#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
@@ -404,7 +439,7 @@ do \
} \
while (0)
extern uint8 *dmem_addr PARAMS ((uint32));
extern uint8 *dmem_addr (uint16 offset);
extern uint8 *imem_addr PARAMS ((uint32));
extern bfd_vma decode_pc PARAMS ((void));
@@ -434,13 +469,6 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
#define READ_64(x) get_longlong(x)
#define WRITE_64(addr,data) write_longlong(addr,data)
#define IMAP0 RW(0xff00)
#define IMAP1 RW(0xff02)
#define DMAP RW(0xff04)
#define SET_IMAP0(x) SW(0xff00,x)
#define SET_IMAP1(x) SW(0xff02,x)
#define SET_DMAP(x) SW(0xff04,x)
#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
#define RIE_VECTOR_START 0xffc2
@@ -449,4 +477,9 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
#define DBT_VECTOR_START 0xffd4
#define SDBT_VECTOR_START 0xffd5
extern reg_t move_to_cr PARAMS ((int cr, reg_t mask, reg_t val));
/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
(VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
PSW is masked for zero bits. */
extern reg_t move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p);

921
sim/d10v/interp.c
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File diff suppressed because it is too large Load Diff

28
sim/d10v/simops.c
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@@ -56,10 +56,13 @@ enum {
| PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT),
/* The following bits in the PSW _can't_ be set by instructions such
as mvtc. */
PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
};
reg_t
move_to_cr (int cr, reg_t mask, reg_t val)
move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
{
/* A MASK bit is set when the corresponding bit in the CR should
be left alone */
@@ -67,13 +70,18 @@ move_to_cr (int cr, reg_t mask, reg_t val)
switch (cr)
{
case PSW_CR:
val &= PSW_MASK;
if (psw_hw_p)
val &= PSW_HW_MASK;
else
val &= PSW_MASK;
if ((mask & PSW_SM_BIT) == 0)
{
int new_sm = (val & PSW_SM_BIT) != 0;
SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
if (PSW_SM != new_sm)
SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
int new_psw_sm = (val & PSW_SM_BIT) != 0;
/* save old SP */
SET_HELD_SP (PSW_SM, GPR (SP_IDX));
if (PSW_SM != new_psw_sm)
/* restore new SP */
SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
}
if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
{
@@ -91,7 +99,11 @@ move_to_cr (int cr, reg_t mask, reg_t val)
break;
case BPSW_CR:
case DPSW_CR:
val &= PSW_MASK;
/* Just like PSW, mask things like DM out. */
if (psw_hw_p)
val &= PSW_HW_MASK;
else
val &= PSW_MASK;
break;
case MOD_S_CR:
case MOD_E_CR:
@@ -1096,7 +1108,7 @@ OP_5F20 ()
trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
SET_DPC (PC + 1);
SET_DPSW (PSW);
SET_PSW (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT));
SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (DBT_VECTOR_START);
trace_output_void ();
}

5
sim/mips/ChangeLog
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@@ -1,3 +1,8 @@
1999-11-11 Andrew Haley <aph@cygnus.com>
* interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
instructions.
Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
* mips.igen (MULT): Correct previous mis-applied patch.

9
sim/mips/interp.c
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@@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd,
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
if (((code == 0x00) || (code == 0x04)) && tail == 0)
if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
|| (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
&& tail == 0)
{
/* M[TF]C0 - 32 bit word */
/* Clear double/single coprocessor move bit. */
code &= ~1;
/* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{

9
sim/testsuite/d10v-elf/ChangeLog
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@@ -1,3 +1,12 @@
Fri Oct 29 18:36:34 1999 Andrew Cagney <cagney@b1.cygnus.com>
* t-mvtc.s: Check that the user can not modify the DM bit in the
BPSW or DPSW.
Thu Oct 28 01:47:26 1999 Andrew Cagney <cagney@b1.cygnus.com>
* t-mvtc.s: Update. Check that user can not modify DM bit.
Wed Sep 8 19:34:55 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* t-ld-st.s: New file.

56
sim/testsuite/d10v-elf/t-mvtc.s
View File

@@ -17,7 +17,7 @@
checkpsw2 4 PSW_DB
loadpsw2 PSW_DM
checkpsw2 5 PSW_DM
checkpsw2 5 0 ;; PSW_DM
loadpsw2 PSW_IE
checkpsw2 6 PSW_IE
@@ -65,17 +65,65 @@
mvfc r7, cr11
check 18 r7 0xbeee
;;; Check that certain bits of the DPSW and BPSW are hardwired to zero
;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
psw_ffff:
ldi r6, 0xffff
mvtc r6, psw
mvfc r7, psw
check 18 r7 0xb7cd
bpsw_ffff:
ldi r6, 0xffff
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0xbfcd
check 18 r7 0xb7cd
dpsw_ffff:
ldi r6, 0xffff
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0xbfcd
check 18 r7 0xb7cd
;;; Another check. Very similar
psw_dfff:
ldi r6, 0xdfff
mvtc r6, psw
mvfc r7, psw
check 18 r7 0x97cd
bpsw_dfff:
ldi r6, 0xdfff
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0x97cd
dpsw_dfff:
ldi r6, 0xdfff
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0x97cd
;;; And again.
psw_8005:
ldi r6, 0x8005
mvtc r6, psw
mvfc r7, psw
check 18 r7 0x8005
bpsw_8005:
ldi r6, 0x8005
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0x8005
dpsw_8005:
ldi r6, 0x8005
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0x8005
exit0