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Display system registers by their names when disassembling RL78 instructions.

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PR binutils/19158
opcodes	* rl78-decode.opc: Add 's' print operator to instructions that
	access system registers.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78_common): Decode all system
	registers.

tests	* gas/rl78/pr19158.s: New test source file.
	* gas/rl78/pr19158.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
This commit is contained in:
Vinay Kumar
2015-10-27 14:49:02 +00:00
committed by Nick Clifton
parent 02f12cd466
commit 4666280441
8 changed files with 81 additions and 13 deletions
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18
opcodes/rl78-decode.c
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@@ -2477,14 +2477,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xab:
{
/** 0110 0001 1010 1011 xch %0, %1 */
/** 0110 0001 1010 1011 xch %0, %s1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x %02x\n",
"/** 0110 0001 1010 1011 xch %0, %1 */",
op[0], op[1]);
}
SYNTAX("xch %0, %1");
SYNTAX("xch %0, %s1");
#line 1232 "rl78-decode.opc"
ID(xch); DR(A); SM(None, SFR);
@@ -4566,14 +4566,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x9e:
{
/** 1001 1110 mov %0, %1 */
/** 1001 1110 mov %s0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1001 1110 mov %0, %1 */",
op[0]);
}
SYNTAX("mov %0, %1");
SYNTAX("mov %s0, %1");
#line 780 "rl78-decode.opc"
ID(mov); DM(None, SFR); SR(A);
@@ -4979,14 +4979,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xbe:
{
/** 1011 1110 movw %0, %1 */
/** 1011 1110 movw %s0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1011 1110 movw %0, %1 */",
"/** 1011 1110 movw %s0, %1 */",
op[0]);
}
SYNTAX("movw %0, %1");
SYNTAX("movw %s0, %1");
#line 901 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SR(AX);
@@ -5098,14 +5098,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xcb:
{
/** 1100 1011 movw %0, #%1 */
/** 1100 1011 movw %s0, #%1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1100 1011 movw %0, #%1 */",
op[0]);
}
SYNTAX("movw %0, #%1");
SYNTAX("movw %s0, #%1");
#line 898 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SC(IMMU(2));