bpf: correct neg and neg32 instruction encoding

The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header
source bit, despite operating on registers.  If BPF_SRC_X (=1) is set,
the instructions are rejected by the kernel.

Because of this there are also no neg/neg32 instructions which operate
on immediates, so remove them.

bd434cc4d9 was a similar fix in the old
CGEN-based port, but was not carried forward in the new port.

include/
	* opcode/bpf.h (enum bpf_insn_id): Remove spurious entries
	BPF_INSN_NEGI and BPF_INSN_NEG32I.

opcodes/
	* bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I
	instructions.

gas/
	* doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and
	neg32 instructions operating on immediates.
	* testsuite/gas/bpf/alu.s: Adapt accordingly.
	* testsuite/gas/bpf/alu.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise
	* testsuite/gas/bpf/alu32.s: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.

gas/doc/c-bpf.texi

@@ -256,17 +256,9 @@ registers.
 64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
 
 @item neg rd
-@itemx neg rd, imm32
 @itemx rd = - rd
-@itemx rd = - imm32
 64-bit arithmetic negation.
 
-Note that in the @code{rd = - imm32} syntax there must be at least
-one white space between @code{-} and @code{imm32}.  Otherwise the
-instruction is parsed as a @code{mov rd, imm32} instruction with a
-negative 32-bit immediate.  This is a consequence of a syntactic
-ambiguity in the pseudoc syntax.
-
 @item mov rd, rs
 @itemx mov rd, imm32
 @itemx rd = rs
@@ -363,17 +355,9 @@ in the same instruction.
 32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
 
 @item neg32 rd
-@itemx neg32 rd, imm32
 @itemx rd = - rd
-@itemx rd = - imm32
 32-bit arithmetic negation.
 
-Note that in the @code{rd = - imm32} syntax there must be at least
-one white space between @code{-} and @code{imm32}.  Otherwise the
-instruction is parsed as a @code{mov32 rd, imm32} instruction with a
-negative 32-bit immediate.  This is a consequence of a syntactic
-ambiguity in the pseudoc syntax.
-
 @item mov32 rd, rs
 @itemx mov32 rd, imm32
 @itemx rd = rs

gas/testsuite/gas/bpf/alu-be-pseudoc.d

@@ -56,7 +56,7 @@ Disassembly of section .text:
  168:	c7 30 00 00 ff ff fd 66 	r3 s>>=0xfffffd66
  170:	c7 40 00 00 7e ad be ef 	r4 s>>=0x7eadbeef
  178:	cf 56 00 00 00 00 00 00 	r5 s>>=r6
- 180:	8f 20 00 00 00 00 00 00 	r2=-r2
+ 180:	87 20 00 00 00 00 00 00 	r2=-r2
  188:	d4 90 00 00 00 00 00 10 	r9=le16 r9
  190:	d4 80 00 00 00 00 00 20 	r8=le32 r8
  198:	d4 70 00 00 00 00 00 40 	r7=le64 r7
@@ -69,4 +69,3 @@ Disassembly of section .text:
  1d0:	d7 10 00 00 00 00 00 10 	r1 = bswap16 r1
  1d8:	d7 20 00 00 00 00 00 20 	r2 = bswap32 r2
  1e0:	d7 30 00 00 00 00 00 40 	r3 = bswap64 r3
- 1e8:	b7 10 00 00 ff ff f1 00 	r1=0xfffff100

gas/testsuite/gas/bpf/alu-be.d

@@ -56,7 +56,7 @@ Disassembly of section .text:
  168:	c7 30 00 00 ff ff fd 66 	arsh %r3,0xfffffd66
  170:	c7 40 00 00 7e ad be ef 	arsh %r4,0x7eadbeef
  178:	cf 56 00 00 00 00 00 00 	arsh %r5,%r6
- 180:	8f 20 00 00 00 00 00 00 	neg %r2
+ 180:	87 20 00 00 00 00 00 00 	neg %r2
  188:	d4 90 00 00 00 00 00 10 	endle %r9,16
  190:	d4 80 00 00 00 00 00 20 	endle %r8,32
  198:	d4 70 00 00 00 00 00 40 	endle %r7,64
@@ -69,4 +69,3 @@ Disassembly of section .text:
  1d0:	d7 10 00 00 00 00 00 10 	bswap %r1,16
  1d8:	d7 20 00 00 00 00 00 20 	bswap %r2,32
  1e0:	d7 30 00 00 00 00 00 40 	bswap %r3,64
- 1e8:	87 10 00 00 00 00 0f 00 	neg %r1,0xf00

gas/testsuite/gas/bpf/alu-pseudoc.d

@@ -56,7 +56,7 @@ Disassembly of section .text:
  168:	c7 03 00 00 66 fd ff ff 	r3 s>>=0xfffffd66
  170:	c7 04 00 00 ef be ad 7e 	r4 s>>=0x7eadbeef
  178:	cf 65 00 00 00 00 00 00 	r5 s>>=r6
- 180:	8f 02 00 00 00 00 00 00 	r2=-r2
+ 180:	87 02 00 00 00 00 00 00 	r2=-r2
  188:	d4 09 00 00 10 00 00 00 	r9=le16 r9
  190:	d4 08 00 00 20 00 00 00 	r8=le32 r8
  198:	d4 07 00 00 40 00 00 00 	r7=le64 r7
@@ -69,4 +69,3 @@ Disassembly of section .text:
  1d0:	d7 01 00 00 10 00 00 00 	r1 = bswap16 r1
  1d8:	d7 02 00 00 20 00 00 00 	r2 = bswap32 r2
  1e0:	d7 03 00 00 40 00 00 00 	r3 = bswap64 r3
- 1e8:	b7 01 00 00 00 f1 ff ff 	r1=0xfffff100

gas/testsuite/gas/bpf/alu-pseudoc.s

@@ -61,7 +61,3 @@
         r1 = bswap16 r1
         r2 = bswap32 r2
         r3 = bswap64 r3
-        ;; Note that the next instruction gets processed by the GAS
-        ;; preprocessor into r1 =-0xf00, which parses into a %dr = %i32
-        ;; instruction instead of a neg :/
-	r1 = - 0xf00

gas/testsuite/gas/bpf/alu.d

@@ -56,7 +56,7 @@ Disassembly of section .text:
  168:	c7 03 00 00 66 fd ff ff 	arsh %r3,0xfffffd66
  170:	c7 04 00 00 ef be ad 7e 	arsh %r4,0x7eadbeef
  178:	cf 65 00 00 00 00 00 00 	arsh %r5,%r6
- 180:	8f 02 00 00 00 00 00 00 	neg %r2
+ 180:	87 02 00 00 00 00 00 00 	neg %r2
  188:	d4 09 00 00 10 00 00 00 	endle %r9,16
  190:	d4 08 00 00 20 00 00 00 	endle %r8,32
  198:	d4 07 00 00 40 00 00 00 	endle %r7,64
@@ -69,4 +69,3 @@ Disassembly of section .text:
  1d0:	d7 01 00 00 10 00 00 00 	bswap %r1,16
  1d8:	d7 02 00 00 20 00 00 00 	bswap %r2,32
  1e0:	d7 03 00 00 40 00 00 00 	bswap %r3,64
- 1e8:	87 01 00 00 00 0f 00 00 	neg %r1,0xf00

gas/testsuite/gas/bpf/alu.s

@@ -61,4 +61,3 @@
         bswap   %r1, 16
         bswap   %r2, 32
         bswap   %r3, 64
-        neg     %r1, 0xf00

gas/testsuite/gas/bpf/alu32-be-pseudoc.d

@@ -56,8 +56,7 @@ Disassembly of section .text:
  168:	c4 30 00 00 ff ff fd 66 	w3 s>>=0xfffffd66
  170:	c4 40 00 00 7e ad be ef 	w4 s>>=0x7eadbeef
  178:	cc 56 00 00 00 00 00 00 	w5 s>>=w6
- 180:	8c 20 00 00 00 00 00 00 	w2=-w2
+ 180:	84 20 00 00 00 00 00 00 	w2=-w2
  188:	bc 12 00 08 00 00 00 00 	w1 = \(s8\) w2
  190:	bc 12 00 10 00 00 00 00 	w1 = \(s16\) w2
  198:	bc 12 00 20 00 00 00 00 	w1 = \(s32\) w2
- 1a0:	b4 10 00 00 ff ff f1 00 	w1=0xfffff100

gas/testsuite/gas/bpf/alu32-be.d

@@ -56,8 +56,7 @@ Disassembly of section .text:
  168:	c4 30 00 00 ff ff fd 66 	arsh32 %r3,0xfffffd66
  170:	c4 40 00 00 7e ad be ef 	arsh32 %r4,0x7eadbeef
  178:	cc 56 00 00 00 00 00 00 	arsh32 %r5,%r6
- 180:	8c 20 00 00 00 00 00 00 	neg32 %r2
+ 180:	84 20 00 00 00 00 00 00 	neg32 %r2
  188:	bc 12 00 08 00 00 00 00 	movs32 %r1,%r2,8
  190:	bc 12 00 10 00 00 00 00 	movs32 %r1,%r2,16
  198:	bc 12 00 20 00 00 00 00 	movs32 %r1,%r2,32
- 1a0:	84 10 00 00 00 00 0f 00 	neg32 %r1,0xf00

gas/testsuite/gas/bpf/alu32-pseudoc.d

@@ -56,8 +56,7 @@ Disassembly of section .text:
  168:	c4 03 00 00 66 fd ff ff 	w3 s>>=0xfffffd66
  170:	c4 04 00 00 ef be ad 7e 	w4 s>>=0x7eadbeef
  178:	cc 65 00 00 00 00 00 00 	w5 s>>=w6
- 180:	8c 02 00 00 00 00 00 00 	w2=-w2
+ 180:	84 02 00 00 00 00 00 00 	w2=-w2
  188:	bc 21 08 00 00 00 00 00 	w1 = \(s8\) w2
  190:	bc 21 10 00 00 00 00 00 	w1 = \(s16\) w2
  198:	bc 21 20 00 00 00 00 00 	w1 = \(s32\) w2
- 1a0:	b4 01 00 00 00 f1 ff ff 	w1=0xfffff100

gas/testsuite/gas/bpf/alu32-pseudoc.s

@@ -52,7 +52,3 @@
         w1 = (s8) w2
         w1 = (s16) w2
         w1 = (s32) w2
-        ;; Note that the next instruction gets processed by the GAS
-        ;; preprocessor into w1 =-0xf00, which parses into a %dw = %i32
-        ;; instruction instead of a neg :/
-	w1 = - 0xf00

gas/testsuite/gas/bpf/alu32.d

@@ -56,8 +56,7 @@ Disassembly of section .text:
  168:	c4 03 00 00 66 fd ff ff 	arsh32 %r3,0xfffffd66
  170:	c4 04 00 00 ef be ad 7e 	arsh32 %r4,0x7eadbeef
  178:	cc 65 00 00 00 00 00 00 	arsh32 %r5,%r6
- 180:	8c 02 00 00 00 00 00 00 	neg32 %r2
+ 180:	84 02 00 00 00 00 00 00 	neg32 %r2
  188:	bc 21 08 00 00 00 00 00 	movs32 %r1,%r2,8
  190:	bc 21 10 00 00 00 00 00 	movs32 %r1,%r2,16
  198:	bc 21 20 00 00 00 00 00 	movs32 %r1,%r2,32
- 1a0:	84 01 00 00 00 0f 00 00 	neg32 %r1,0xf00

gas/testsuite/gas/bpf/alu32.s

@@ -52,4 +52,3 @@
         movs32  %r1,%r2,8
         movs32  %r1,%r2,16
         movs32  %r1,%r2,32
-        neg32   %r1, 0xf00

include/opcode/bpf.h

@@ -168,7 +168,7 @@ enum bpf_insn_id
   BPF_INSN_SMODR, BPF_INSN_SMODI, BPF_INSN_DIVR, BPF_INSN_DIVI,
   BPF_INSN_MODR, BPF_INSN_MODI, BPF_INSN_ORR, BPF_INSN_ORI,
   BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,
-  BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,
+  BPF_INSN_NEGR, BPF_INSN_LSHR, BPF_INSN_LSHI,
   BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,
   BPF_INSN_MOVS8R, BPF_INSN_MOVS16R, BPF_INSN_MOVS32R,
   BPF_INSN_MOVR, BPF_INSN_MOVI,
@@ -178,7 +178,7 @@ enum bpf_insn_id
   BPF_INSN_SMOD32R, BPF_INSN_SMOD32I, BPF_INSN_DIV32R, BPF_INSN_DIV32I,
   BPF_INSN_MOD32R, BPF_INSN_MOD32I, BPF_INSN_OR32R, BPF_INSN_OR32I,
   BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,
-  BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
+  BPF_INSN_NEG32R, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
   BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
   BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R,
   BPF_INSN_MOV32R, BPF_INSN_MOV32I,

opcodes/bpf-opc.c

@@ -74,8 +74,6 @@ const struct bpf_opcode bpf_opcodes[] =
   {BPF_INSN_XORI, "xor%W%dr , %i32", "%dr ^= %i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_K},
   {BPF_INSN_NEGR, "neg%W%dr", "%dr = - %dr",
-   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_X},
-  {BPF_INSN_NEGI, "neg%W%dr , %i32", "%dr = -%W%i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_K},
   {BPF_INSN_LSHR, "lsh%W%dr , %sr", "%dr <<= %sr",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_X},
@@ -142,8 +140,6 @@ const struct bpf_opcode bpf_opcodes[] =
   {BPF_INSN_XOR32I, "xor32%W%dr , %i32", "%dw ^= %i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_K},
   {BPF_INSN_NEG32R, "neg32%W%dr", "%dw = - %dw",
-   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_X},
-  {BPF_INSN_NEG32I, "neg32%W%dr , %i32", "%dw = -%W%i32",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_K},
   {BPF_INSN_LSH32R, "lsh32%W%dr , %sr", "%dw <<= %sw",
    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_X},