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NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.

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First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
This commit is contained in:
Kuan-Lin Chen
2014-09-10 09:46:32 +08:00
parent 5b636fed3a
commit 40c7a7cb74
8 changed files with 2355 additions and 1858 deletions
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4
include/opcode/ChangeLog
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@@ -1,3 +1,7 @@
2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* nds32.h: Add new opcode declaration.
2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
Matthew Fortune <matthew.fortune@imgtec.com>

10
include/opcode/nds32.h
View File

@@ -29,6 +29,7 @@
#define REG_R16 16
#define REG_R20 20
#define REG_TA 15
#define REG_TP 27
#define REG_FP 28
#define REG_GP 29
#define REG_LP 30
@@ -358,12 +359,13 @@ enum n32_opcodes
N32_ALU2_SUB_SC,
N32_ALU2_ADD_WC,
N32_ALU2_SUB_WC,
N32_ALU2_0x14,
N32_ALU2_KMxy,
N32_ALU2_0x15,
N32_ALU2_0x16,
N32_ALU2_FFZMISM,
N32_ALU2_QADD = 0x18,
N32_ALU2_QSUB,
N32_ALU2_KADD = 0x18,
N32_ALU2_KSUB,
N32_ALU2_KSLRA,
N32_ALU2_MFUSR = 0x20,
N32_ALU2_MTUSR,
N32_ALU2_0x22,
@@ -459,7 +461,7 @@ enum n32_opcodes
N32_MISC_TLBOP,
N32_MISC_0xf,
/* bit[0;4] */
/* bit[0:4] */
N32_SIMD_PBSAD = 0,
N32_SIMD_PBSADA = 1,