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[OPCODES][ARM]Fix mask for a few coprocessor opcodes.

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opcodes/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
	vrint(mpna).

gas/

2016-02-24  Renlin Li  <renlin.li@arm.com>

	* testsuite/gas/arm/mask_1.d: New.
	* testsuite/gas/arm/mask_1.s: New.
This commit is contained in:
Renlin Li
2016-02-24 13:55:30 +00:00
parent 8afc7bea40
commit 3e309328e8
5 changed files with 63 additions and 8 deletions
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16
opcodes/arm-dis.c
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@@ -820,17 +820,17 @@ static const struct opcode32 coprocessor_opcodes[] =
/* FP v5. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
@@ -840,9 +840,9 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },