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aarch64: [SME] Add SME mode selection and state access instructions

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This patch is adding new SME mode selection and state access instructions:
* Add SMSTART and SMSTOP instructions.
* Add SVCR system register.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sme_sm_za): New parser.
	(parse_operands): New parser.
	* testsuite/gas/aarch64/sme-8-illegal.d: New test.
	* testsuite/gas/aarch64/sme-8-illegal.l: New test.
	* testsuite/gas/aarch64/sme-8-illegal.s: New test.
	* testsuite/gas/aarch64/sme-8.d: New test.
	* testsuite/gas/aarch64/sme-8.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_SME_SM_ZA.
	(enum aarch64_insn_class): New instruction classes
	sme_start and sme_stop.

opcodes/ChangeLog:

	* aarch64-asm.c (aarch64_ins_pstatefield): New inserter.
	(aarch64_ins_sme_sm_za): New inserter.
	* aarch64-dis.c (aarch64_ext_imm): New extractor.
	(aarch64_ext_pstatefield): New extractor.
	(aarch64_ext_sme_sm_za): New extractor.
	* aarch64-opc.c (operand_general_constraint_met_p):
	New pstatefield value for SME instructions.
	(aarch64_print_operand): Printout for OPND_SME_SM_ZA.
	(SR_SME): New register SVCR.
	* aarch64-opc.h (F_REG_IN_CRM): New register endcoding.
	* aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding.
	(PSTATE_ENCODE_CRM): Encode CRm field.
	(PSTATE_DECODE_CRM): Decode CRm field.
	(PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field.
	(PSTATE_DECODE_CRM_IMM): Decode CRm immediate field.
	(PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate
	field.
	* aarch64-tbl.h (struct aarch64_opcode): New SMSTART
	and SMSTOP instructions.
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.
This commit is contained in:
Przemyslaw Wirkus
2021-11-17 20:15:13 +00:00
parent 01a4d08220
commit 3dd032c5fb
17 changed files with 1775 additions and 1531 deletions
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3
include/opcode/aarch64.h
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@@ -454,6 +454,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
@@ -621,6 +622,8 @@ enum aarch64_insn_class
sme_misc,
sme_ldr,
sme_str,
sme_start,
sme_stop,
sve_cpy,
sve_index,
sve_limm,