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bpf: simulator: correct div, mod insn semantics

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The div and mod eBPF instructions are unsigned, but the semantic
specification for the simulator incorrectly used signed operators.
Correct them to unsigned versions, and correct the ALU tests in
the simulator (which incorrectly assumed signed semantics).

Tested in bpf-unknown-none.

cpu/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf.cpu (define-alu-instructions): Correct semantic operators
	for div, mod to unsigned versions.

sim/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf/sem-be.c: Regenerate.
	* bpf/sem-le.c: Likewise.

sim/testsuite/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* sim/bpf/alu.s: Correct div and mod tests.
	* sim/bpf/alu32.s: Likewise.
This commit is contained in:
David Faust
2020-09-08 11:39:07 -07:00
parent 790147a9e9
commit 3ad6c19423
8 changed files with 73 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
sim/bpf/sem-le.c
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@@ -461,7 +461,7 @@ SEM_FN_NAME (bpfbf_ebpfle,divile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
DI opval = UDIVDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -482,7 +482,7 @@ SEM_FN_NAME (bpfbf_ebpfle,divrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
DI opval = UDIVDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -503,7 +503,7 @@ SEM_FN_NAME (bpfbf_ebpfle,div32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
USI opval = UDIVSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
@@ -524,7 +524,7 @@ SEM_FN_NAME (bpfbf_ebpfle,div32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
USI opval = UDIVSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
@@ -881,7 +881,7 @@ SEM_FN_NAME (bpfbf_ebpfle,modile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
DI opval = UMODDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -902,7 +902,7 @@ SEM_FN_NAME (bpfbf_ebpfle,modrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
DI opval = UMODDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -923,7 +923,7 @@ SEM_FN_NAME (bpfbf_ebpfle,mod32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
USI opval = UMODSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
@@ -944,7 +944,7 @@ SEM_FN_NAME (bpfbf_ebpfle,mod32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
{
USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
USI opval = UMODSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
CPU (h_gpr[FLD (f_dstle)]) = opval;
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}