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gas/

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2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
	(match_template): Handle operand size for crc32 in SSE4.2.
	(process_suffix): Handle operand type for crc32 in SSE4.2.
	(output_insn): Support SSE4.2.

gas/testsuite/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2.

	* gas/i386/sse4_2.d: New file.
	* gas/i386/sse4_2.s: Likewise.
	* gas/i386/x86-64-sse4_2.d: Likewise.
	* gas/i386/x86-64-sse4_2.s: Likewise.

opcodes/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (CRC32_Fixup): New.
	(PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
	 PREGRP91): New.
	(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
	(threebyte_0x3a_uses_DATA_prefix): Likewise.
	(prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
	PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
	(three_byte_table): Likewise.

	* i386-opc.c (i386_optab): Add SSE4.2 opcodes.

	* gas/config/tc-i386.h (CpuSSE4_2): New.
	(CpuSSE4): Likewise.
	(CpuUnknownFlags): Add CpuSSE4_2.
This commit is contained in:
H.J. Lu
2007-04-18 16:15:55 +00:00
parent 42903f7f59
commit 381d071fc5
12 changed files with 386 additions and 28 deletions
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14
opcodes/i386-opc.c
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@@ -1435,6 +1435,18 @@ const template i386_optab[] =
{"roundsd", 3, 0x660f3a0b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"roundss", 3, 0x660f3a0a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
/* Streaming SIMD extensions 4.2 Instructions. */
{"pcmpgtq", 2, 0x660f3837,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pcmpestri", 3, 0x660f3a61,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"pcmpestrm", 3, 0x660f3a60,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"pcmpistri", 3, 0x660f3a63,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"crc32b", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8|ByteMem, Reg32|Reg64, 0 } },
{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8, Reg32|Reg64, 0 } },
{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } },
{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } },
/* AMD 3DNow! instructions. */
{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
@@ -1497,7 +1509,7 @@ const template i386_optab[] =
{"insertq", 4, 0xf20f78, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM, RegXMM} },
/* ABM instructions */
{"popcnt", 2, 0xf30fb8, X, CpuABM, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"popcnt", 2, 0xf30fb8, X, CpuABM|CpuSSE4_2, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"lzcnt", 2, 0xf30fbd, X, CpuABM, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },