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* gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.

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(NEON_ENC_FPV8_): New define.
	(do_vfp_nsyn_fpv8): New function.
	(do_vsel): Likewise.
	(insns): Add VSEL instructions.
	* gas/testsuite/gas/arm/armv8-a+fp.d: New testcase.
	* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add VSEL.
	(print_insn_coprocessor): Add new %<>c bitfield format
	specifier.
This commit is contained in:
Matthew Gretton-Dann
2012-08-24 08:06:36 +00:00
parent 9eb6c0f132
commit 33399f071c
7 changed files with 140 additions and 1 deletions
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30
opcodes/arm-dis.c
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@@ -102,6 +102,7 @@ struct opcode16
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitfield>c print as a condition code (for vsel)
%<bitfield>r print as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
%<bitfield>ru as %<>r but each u register must be unique.
@@ -486,6 +487,10 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
/* FP v5. */
{FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
{ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
@@ -2198,6 +2203,31 @@ print_insn_coprocessor (bfd_vma pc,
func (stream, "0x%lx", (value & 0xffffffffUL));
break;
case 'c':
switch (value)
{
case 0:
func (stream, "eq");
break;
case 1:
func (stream, "vs");
break;
case 2:
func (stream, "ge");
break;
case 3:
func (stream, "gt");
break;
default:
func (stream, "??");
break;
}
break;
case '`':
c++;
if (value == 0)