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arc: Improve error messages when assembling

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gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Add error messages.
	* testsuite/gas/arc/add_s-err.s: Update test.
	* testsuite/gas/arc/asm-errors.err: Likewise.
	* testsuite/gas/arc/cpu-em-err.s: Likewise.
	* testsuite/gas/arc/hregs-err.s: Likewise.
	* testsuite/gas/arc/warn.s: Likewise.
This commit is contained in:
Claudiu Zissulescu
2020-07-07 16:01:48 +03:00
parent f337259fbd
commit 3128916d88
7 changed files with 63 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@@ -1,3 +1,12 @@
2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): Add error messages.
* testsuite/gas/arc/add_s-err.s: Update test.
* testsuite/gas/arc/asm-errors.err: Likewise.
* testsuite/gas/arc/cpu-em-err.s: Likewise.
* testsuite/gas/arc/hregs-err.s: Likewise.
* testsuite/gas/arc/warn.s: Likewise.
2020-07-07 H.J. Lu <hongjiu.lu@intel.com> 2020-07-07 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26212 PR gas/26212

60
gas/config/tc-arc.c
View File

@@ -1758,8 +1758,9 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
int ntok = *pntok; int ntok = *pntok;
int got_cpu_match = 0; int got_cpu_match = 0;
expressionS bktok[MAX_INSN_ARGS]; expressionS bktok[MAX_INSN_ARGS];
int bkntok; int bkntok, maxerridx = 0;
expressionS emptyE; expressionS emptyE;
const char *tmpmsg = NULL;
arc_opcode_hash_entry_iterator_init (&iter); arc_opcode_hash_entry_iterator_init (&iter);
memset (&emptyE, 0, sizeof (emptyE)); memset (&emptyE, 0, sizeof (emptyE));
@@ -1806,7 +1807,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
{ {
case ARC_OPERAND_ADDRTYPE: case ARC_OPERAND_ADDRTYPE:
{ {
*errmsg = NULL; tmpmsg = NULL;
/* Check to be an address type. */ /* Check to be an address type. */
if (tok[tokidx].X_op != O_addrtype) if (tok[tokidx].X_op != O_addrtype)
@@ -1817,8 +1818,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
address type. */ address type. */
gas_assert (operand->insert != NULL); gas_assert (operand->insert != NULL);
(*operand->insert) (0, tok[tokidx].X_add_number, (*operand->insert) (0, tok[tokidx].X_add_number,
errmsg); &tmpmsg);
if (*errmsg != NULL) if (tmpmsg != NULL)
goto match_failed; goto match_failed;
} }
break; break;
@@ -1844,11 +1845,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Special handling? */ /* Special handling? */
if (operand->insert) if (operand->insert)
{ {
*errmsg = NULL; tmpmsg = NULL;
(*operand->insert)(0, (*operand->insert)(0,
regno (tok[tokidx].X_add_number), regno (tok[tokidx].X_add_number),
errmsg); &tmpmsg);
if (*errmsg) if (tmpmsg)
{ {
if (operand->flags & ARC_OPERAND_IGNORE) if (operand->flags & ARC_OPERAND_IGNORE)
{ {
@@ -1957,26 +1958,35 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
} }
if (val < min || val > max) if (val < min || val > max)
goto match_failed; {
tmpmsg = _("immediate is out of bounds");
goto match_failed;
}
/* Check alignments. */ /* Check alignments. */
if ((operand->flags & ARC_OPERAND_ALIGNED32) if ((operand->flags & ARC_OPERAND_ALIGNED32)
&& (val & 0x03)) && (val & 0x03))
goto match_failed; {
tmpmsg = _("immediate is not 32bit aligned");
goto match_failed;
}
if ((operand->flags & ARC_OPERAND_ALIGNED16) if ((operand->flags & ARC_OPERAND_ALIGNED16)
&& (val & 0x01)) && (val & 0x01))
goto match_failed; {
tmpmsg = _("immediate is not 16bit aligned");
goto match_failed;
}
} }
else if (operand->flags & ARC_OPERAND_NCHK) else if (operand->flags & ARC_OPERAND_NCHK)
{ {
if (operand->insert) if (operand->insert)
{ {
*errmsg = NULL; tmpmsg = NULL;
(*operand->insert)(0, (*operand->insert)(0,
tok[tokidx].X_add_number, tok[tokidx].X_add_number,
errmsg); &tmpmsg);
if (*errmsg) if (tmpmsg)
goto match_failed; goto match_failed;
} }
else if (!(operand->flags & ARC_OPERAND_IGNORE)) else if (!(operand->flags & ARC_OPERAND_IGNORE))
@@ -1997,11 +2007,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
regs |= get_register (tok[tokidx].X_op_symbol); regs |= get_register (tok[tokidx].X_op_symbol);
if (operand->insert) if (operand->insert)
{ {
*errmsg = NULL; tmpmsg = NULL;
(*operand->insert)(0, (*operand->insert)(0,
regs, regs,
errmsg); &tmpmsg);
if (*errmsg) if (tmpmsg)
goto match_failed; goto match_failed;
} }
else else
@@ -2044,7 +2054,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
|| t->X_op == O_absent || t->X_op == O_absent
|| t->X_op == O_register || t->X_op == O_register
|| (t->X_add_number != tok[tokidx].X_add_number)) || (t->X_add_number != tok[tokidx].X_add_number))
goto match_failed; {
tmpmsg = _("operand is not duplicate of the "
"previous one");
goto match_failed;
}
} }
t = &tok[tokidx]; t = &tok[tokidx];
break; break;
@@ -2060,7 +2074,10 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Setup ready for flag parsing. */ /* Setup ready for flag parsing. */
if (!parse_opcode_flags (opcode, nflgs, first_pflag)) if (!parse_opcode_flags (opcode, nflgs, first_pflag))
goto match_failed; {
tmpmsg = _("flag mismatch");
goto match_failed;
}
pr_debug ("flg"); pr_debug ("flg");
/* Possible match -- did we use all of our input? */ /* Possible match -- did we use all of our input? */
@@ -2070,12 +2087,19 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
pr_debug ("\n"); pr_debug ("\n");
return opcode; return opcode;
} }
tmpmsg = _("too many arguments");
match_failed:; match_failed:;
pr_debug ("\n"); pr_debug ("\n");
/* Restore the original parameters. */ /* Restore the original parameters. */
memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok)); memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
ntok = bkntok; ntok = bkntok;
if (tokidx >= maxerridx
&& tmpmsg)
{
maxerridx = tokidx;
*errmsg = tmpmsg;
}
} }
if (*pcpumatch) if (*pcpumatch)

4
gas/testsuite/gas/arc/add_s-err.s
View File

@@ -6,5 +6,5 @@
;; The following insns are accepted by ARCv2 only ;; The following insns are accepted by ARCv2 only
add_s r4,r4,-1 ; { dg-error "Error: register must be either r0-r3 or r12-r15 for instruction" } add_s r4,r4,-1 ; { dg-error "Error: register must be either r0-r3 or r12-r15 for instruction" }
add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s r0,r15,0x20 ; { dg-error "Error: immediate is out of bounds for instruction 'add_s'" }
add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s r1,r15,0x20 ; { dg-error "Error: immediate is out of bounds for instruction 'add_s'" }

6
gas/testsuite/gas/arc/asm-errors.err
View File

@@ -1,6 +1,6 @@
[^:]*: Assembler messages: [^:]*: Assembler messages:
[^:]*:2: Error: inappropriate arguments for opcode 'adc' [^:]*:2: Error: flag mismatch for instruction 'adc'
[^:]*:3: Error: inappropriate arguments for opcode 'adc' [^:]*:3: Error: flag mismatch for instruction 'adc'
[^:]*:4: Error: inappropriate arguments for opcode 'adc' [^:]*:4: Error: flag mismatch for instruction 'adc'
[^:]*:5: Error: extra comma [^:]*:5: Error: extra comma
[^:]*:5: Error: syntax error [^:]*:5: Error: syntax error

2
gas/testsuite/gas/arc/cpu-em-err.s
View File

@@ -1,4 +1,4 @@
;;; Check if .cpu em doesn't have code-density ops. ;;; Check if .cpu em doesn't have code-density ops.
; { dg-do assemble { target arc*-*-* } } ; { dg-do assemble { target arc*-*-* } }
.cpu em .cpu em
sub_s r15,r2,r15 ; { dg-error "Error: inappropriate arguments for opcode 'sub_s'" } sub_s r15,r2,r15 ; { dg-error "Error: register must be SP for instruction 'sub_s'" }

8
gas/testsuite/gas/arc/hregs-err.s
View File

@@ -1,11 +1,11 @@
; { dg-do assemble { target arc*-*-* } } ; { dg-do assemble { target arc*-*-* } }
.cpu HS .cpu HS
.text .text
ld_s r0,[r32,28] ; { dg-error "Error: register must be R1 for instruction 'ld_s'" } ld_s r0,[r32,28] ; { dg-error "Error: register must be GP for instruction 'ld_s'" }
ld_s r0,[r28,28] ld_s r0,[r28,28]
ld_s r1,[r32,28] ; { dg-error "Error: register must be GP for instruction 'ld_s'" } ld_s r1,[r32,28] ; { dg-error "Error: register must be GP for instruction 'ld_s'" }
ld_s r2,[r32,28] ; { dg-error "Error: register must be R1 for instruction 'ld_s'" } ld_s r2,[r32,28] ; { dg-error "Error: register must be PCL for instruction 'ld_s'" }
ld_s r3,[pcl,0x10] ld_s r3,[pcl,0x10]
add_s r0,r0,r32 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" } add_s r0,r0,r32 ; { dg-error "Error: register out of range for instruction 'add_s'" }
add_s r0,r0,r28 add_s r0,r0,r28
mov_s.ne r0,r32 ; { dg-error "Error: inappropriate arguments for opcode 'mov_s'" } mov_s.ne r0,r32 ; { dg-error "Error: register out of range for instruction 'mov_s'" }

4
gas/testsuite/gas/arc/warn.s
View File

@@ -3,9 +3,9 @@
; { dg-do assemble { target arc*-*-* } } ; { dg-do assemble { target arc*-*-* } }
b.d foo b.d foo
mov r0,256 mov r0,256
j.d foo ; { dg-warning "inappropriate arguments for opcode" "inappropriate arguments for opcode" } j.d foo ; { dg-error "Error: flag mismatch for instruction 'j'" }
mov r0,r1 mov r0,r1
foo: foo: