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bpf: opcodes, gas: support for signed register move V4 instructions

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This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
	(BPF_OFFSET16_MOVS16): Likewise.
	(BPF_OFFSET16_MOVS32): Likewise.
	(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R.

opcodes/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
	MOVS32{8,16,32}R instructions.  and MOVS32I instructions.

gas/ChangeLog:

2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.s: Test movs instructions.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu.d: Add expected results.
	* testsuite/gas/bpf/alu32.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
This commit is contained in:
Jose E. Marchesi
2023-07-21 17:22:58 +02:00
parent 01deb24db9
commit 2f3dbc5fb5
18 changed files with 105 additions and 0 deletions
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12
opcodes/bpf-opc.c
View File

@@ -89,6 +89,12 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
{BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
{BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=%w( i8 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
{BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=%w( i16 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
{BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=%w( i32 )%w%sr",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
{BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
{BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32",
@@ -151,6 +157,12 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
{BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
{BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=%w( i8 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
{BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=%w( i16 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
{BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=%w( i32 )%w%sw",
BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
{BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
{BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",