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[AArch64] Support for ARMv8.1a Limited Ordering Regions extension

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2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
include/
  * aarch64.h (AARCH64_FEATURE_LOR): New.

opcodes/
  * aarch64-tbl.h (aarch64_feature_lor): New.
  (LOR): New.
  (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  "stllrb", "stllrh".
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.

gas/
  * config/tc-aarch64.c (aarch64_features): Add "lor".
  * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
  architecture extensions.

gas/testsuite/
  * lor-directive.d: New.
  * lor.d: New.
  * lor.s: New.
This commit is contained in:
Matthew Wahab
2015-06-02 11:29:15 +01:00
committed by Jiong Wang
parent 8d683210f1
commit 290806fd94
14 changed files with 589 additions and 401 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@@ -1,3 +1,9 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "lor".
* doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
architecture extensions.
2015-06-01 Matthew Wahab <matthew.wahab@arm.com> 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_reg): New parameter. Check target * config/tc-aarch64.c (parse_sys_reg): New parameter. Check target

1
gas/config/tc-aarch64.c
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@@ -7400,6 +7400,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)}, {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)}, {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)}, {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
{NULL, AARCH64_ARCH_NONE} {NULL, AARCH64_ARCH_NONE}
}; };

2
gas/doc/c-aarch64.texi
View File

@@ -135,6 +135,8 @@ automatically cause those extensions to be disabled.
@tab Enable Advanced SIMD extensions. This implies @code{fp}. @tab Enable Advanced SIMD extensions. This implies @code{fp}.
@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Privileged Access Never support. @tab Enable Privileged Access Never support.
@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Limited Ordering Regions extensions.
@end multitable @end multitable
@node AArch64 Syntax @node AArch64 Syntax

6
gas/testsuite/ChangeLog
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@@ -1,3 +1,9 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* lor-directive.d: New.
* lor.d: New.
* lor.s: New
2015-06-01 Matthew Wahab <matthew.wahab@arm.com> 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* pan-directive.d: New. * pan-directive.d: New.

25
gas/testsuite/gas/aarch64/lor-directive.d Normal file
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@@ -0,0 +1,25 @@
#objdump: -dr
#as: --defsym DIRECTIVE=1
#source: lor.s
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.text>:
0: 889f7c00 stllr w0, \[x0\]
4: c89f7c00 stllr x0, \[x0\]
8: 889f7c01 stllr w1, \[x0\]
c: c89f7c22 stllr x2, \[x1\]
10: 489f7c43 stllrh w3, \[x2\]
14: 089f7c64 stllrb w4, \[x3\]
18: 089f7fe5 stllrb w5, \[sp\]
1c: 88df7c00 ldlar w0, \[x0\]
20: c8df7c00 ldlar x0, \[x0\]
24: 88df7c01 ldlar w1, \[x0\]
28: c8df7c22 ldlar x2, \[x1\]
2c: 08df7c43 ldlarb w3, \[x2\]
30: 48df7c64 ldlarh w4, \[x3\]
34: 88df7fe5 ldlar w5, \[sp\]

23
gas/testsuite/gas/aarch64/lor.d Normal file
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@@ -0,0 +1,23 @@
#objdump: -dr
#as: -march=armv8-a+lor
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.text>:
0: 889f7c00 stllr w0, \[x0\]
4: c89f7c00 stllr x0, \[x0\]
8: 889f7c01 stllr w1, \[x0\]
c: c89f7c22 stllr x2, \[x1\]
10: 489f7c43 stllrh w3, \[x2\]
14: 089f7c64 stllrb w4, \[x3\]
18: 089f7fe5 stllrb w5, \[sp\]
1c: 88df7c00 ldlar w0, \[x0\]
20: c8df7c00 ldlar x0, \[x0\]
24: 88df7c01 ldlar w1, \[x0\]
28: c8df7c22 ldlar x2, \[x1\]
2c: 08df7c43 ldlarb w3, \[x2\]
30: 48df7c64 ldlarh w4, \[x3\]
34: 88df7fe5 ldlar w5, \[sp\]

43
gas/testsuite/gas/aarch64/lor.s Normal file
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@@ -0,0 +1,43 @@
/* lor.s Test file for AArch64 LOR extension instructions.
Copyright (C) 2015 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
.ifdef DIRECTIVE
.arch_extension lor
.endif
stllr w0, [x0]
stllr x0, [x0]
stllr w1, [x0]
stllr x2, [x1]
stllrh w3, [x2]
stllrb w4, [x3]
stllrb w5, [sp]
ldlar w0, [x0]
ldlar x0, [x0]
ldlar w1, [x0]
ldlar x2, [x1]
ldlarb w3, [x2]
ldlarh w4, [x3]
ldlar w5, [sp]

4
include/opcode/ChangeLog
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@@ -1,3 +1,7 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_LOR): New.
2015-06-01 Matthew Wahab <matthew.wahab@arm.com> 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PAN): New. * aarch64.h (AARCH64_FEATURE_PAN): New.

1
include/opcode/aarch64.h
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@@ -40,6 +40,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
/* Architectures are the sum of the base and extensions. */ /* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \

10
opcodes/ChangeLog
View File

@@ -1,3 +1,13 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_lor): New.
(LOR): New.
(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
"stllrb", "stllrh".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2015-06-01 Matthew Wahab <matthew.wahab@arm.com> 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (F_ARCHEXT): New. * aarch64-opc.c (F_ARCHEXT): New.

250
opcodes/aarch64-asm-2.c
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@@ -155,188 +155,188 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 595: /* ror */ case 595: /* ror */
value = 594; /* --> extr. */ value = 594; /* --> extr. */
break; break;
case 746: /* bic */ case 752: /* bic */
value = 745; /* --> and. */ value = 751; /* --> and. */
break; break;
case 748: /* mov */ case 754: /* mov */
value = 747; /* --> orr. */ value = 753; /* --> orr. */
break; break;
case 751: /* tst */ case 757: /* tst */
value = 750; /* --> ands. */ value = 756; /* --> ands. */
break; break;
case 756: /* uxtw */ case 762: /* uxtw */
case 755: /* mov */ case 761: /* mov */
value = 754; /* --> orr. */ value = 760; /* --> orr. */
break; break;
case 758: /* mvn */ case 764: /* mvn */
value = 757; /* --> orn. */ value = 763; /* --> orn. */
break; break;
case 762: /* tst */ case 768: /* tst */
value = 761; /* --> ands. */ value = 767; /* --> ands. */
break; break;
case 888: /* staddb */ case 894: /* staddb */
value = 792; /* --> ldaddb. */ value = 798; /* --> ldaddb. */
break; break;
case 889: /* staddh */ case 895: /* staddh */
value = 793; /* --> ldaddh. */ value = 799; /* --> ldaddh. */
break; break;
case 890: /* stadd */ case 896: /* stadd */
value = 794; /* --> ldadd. */ value = 800; /* --> ldadd. */
break; break;
case 891: /* staddlb */ case 897: /* staddlb */
value = 796; /* --> ldaddlb. */ value = 802; /* --> ldaddlb. */
break; break;
case 892: /* staddlh */ case 898: /* staddlh */
value = 799; /* --> ldaddlh. */ value = 805; /* --> ldaddlh. */
break; break;
case 893: /* staddl */ case 899: /* staddl */
value = 802; /* --> ldaddl. */ value = 808; /* --> ldaddl. */
break; break;
case 894: /* stclrb */ case 900: /* stclrb */
value = 804; /* --> ldclrb. */ value = 810; /* --> ldclrb. */
break; break;
case 895: /* stclrh */ case 901: /* stclrh */
value = 805; /* --> ldclrh. */ value = 811; /* --> ldclrh. */
break; break;
case 896: /* stclr */ case 902: /* stclr */
value = 806; /* --> ldclr. */ value = 812; /* --> ldclr. */
break; break;
case 897: /* stclrlb */ case 903: /* stclrlb */
value = 808; /* --> ldclrlb. */ value = 814; /* --> ldclrlb. */
break; break;
case 898: /* stclrlh */ case 904: /* stclrlh */
value = 811; /* --> ldclrlh. */ value = 817; /* --> ldclrlh. */
break; break;
case 899: /* stclrl */ case 905: /* stclrl */
value = 814; /* --> ldclrl. */ value = 820; /* --> ldclrl. */
break; break;
case 900: /* steorb */ case 906: /* steorb */
value = 816; /* --> ldeorb. */ value = 822; /* --> ldeorb. */
break; break;
case 901: /* steorh */ case 907: /* steorh */
value = 817; /* --> ldeorh. */ value = 823; /* --> ldeorh. */
break; break;
case 902: /* steor */ case 908: /* steor */
value = 818; /* --> ldeor. */ value = 824; /* --> ldeor. */
break; break;
case 903: /* steorlb */ case 909: /* steorlb */
value = 820; /* --> ldeorlb. */ value = 826; /* --> ldeorlb. */
break; break;
case 904: /* steorlh */ case 910: /* steorlh */
value = 823; /* --> ldeorlh. */ value = 829; /* --> ldeorlh. */
break; break;
case 905: /* steorl */ case 911: /* steorl */
value = 826; /* --> ldeorl. */ value = 832; /* --> ldeorl. */
break; break;
case 906: /* stsetb */ case 912: /* stsetb */
value = 828; /* --> ldsetb. */ value = 834; /* --> ldsetb. */
break; break;
case 907: /* stseth */ case 913: /* stseth */
value = 829; /* --> ldseth. */ value = 835; /* --> ldseth. */
break; break;
case 908: /* stset */ case 914: /* stset */
value = 830; /* --> ldset. */ value = 836; /* --> ldset. */
break; break;
case 909: /* stsetlb */ case 915: /* stsetlb */
value = 832; /* --> ldsetlb. */ value = 838; /* --> ldsetlb. */
break; break;
case 910: /* stsetlh */ case 916: /* stsetlh */
value = 835; /* --> ldsetlh. */ value = 841; /* --> ldsetlh. */
break; break;
case 911: /* stsetl */ case 917: /* stsetl */
value = 838; /* --> ldsetl. */ value = 844; /* --> ldsetl. */
break; break;
case 912: /* stsmaxb */ case 918: /* stsmaxb */
value = 840; /* --> ldsmaxb. */ value = 846; /* --> ldsmaxb. */
break; break;
case 913: /* stsmaxh */ case 919: /* stsmaxh */
value = 841; /* --> ldsmaxh. */ value = 847; /* --> ldsmaxh. */
break; break;
case 914: /* stsmax */ case 920: /* stsmax */
value = 842; /* --> ldsmax. */ value = 848; /* --> ldsmax. */
break; break;
case 915: /* stsmaxlb */ case 921: /* stsmaxlb */
value = 844; /* --> ldsmaxlb. */ value = 850; /* --> ldsmaxlb. */
break; break;
case 916: /* stsmaxlh */ case 922: /* stsmaxlh */
value = 847; /* --> ldsmaxlh. */ value = 853; /* --> ldsmaxlh. */
break; break;
case 917: /* stsmaxl */ case 923: /* stsmaxl */
value = 850; /* --> ldsmaxl. */ value = 856; /* --> ldsmaxl. */
break; break;
case 918: /* stsminb */ case 924: /* stsminb */
value = 852; /* --> ldsminb. */ value = 858; /* --> ldsminb. */
break; break;
case 919: /* stsminh */ case 925: /* stsminh */
value = 853; /* --> ldsminh. */ value = 859; /* --> ldsminh. */
break; break;
case 920: /* stsmin */ case 926: /* stsmin */
value = 854; /* --> ldsmin. */ value = 860; /* --> ldsmin. */
break; break;
case 921: /* stsminlb */ case 927: /* stsminlb */
value = 856; /* --> ldsminlb. */ value = 862; /* --> ldsminlb. */
break; break;
case 922: /* stsminlh */ case 928: /* stsminlh */
value = 859; /* --> ldsminlh. */ value = 865; /* --> ldsminlh. */
break; break;
case 923: /* stsminl */ case 929: /* stsminl */
value = 862; /* --> ldsminl. */ value = 868; /* --> ldsminl. */
break; break;
case 924: /* stumaxb */ case 930: /* stumaxb */
value = 864; /* --> ldumaxb. */ value = 870; /* --> ldumaxb. */
break; break;
case 925: /* stumaxh */ case 931: /* stumaxh */
value = 865; /* --> ldumaxh. */ value = 871; /* --> ldumaxh. */
break; break;
case 926: /* stumax */ case 932: /* stumax */
value = 866; /* --> ldumax. */ value = 872; /* --> ldumax. */
break; break;
case 927: /* stumaxlb */ case 933: /* stumaxlb */
value = 868; /* --> ldumaxlb. */ value = 874; /* --> ldumaxlb. */
break; break;
case 928: /* stumaxlh */ case 934: /* stumaxlh */
value = 871; /* --> ldumaxlh. */ value = 877; /* --> ldumaxlh. */
break; break;
case 929: /* stumaxl */ case 935: /* stumaxl */
value = 874; /* --> ldumaxl. */ value = 880; /* --> ldumaxl. */
break; break;
case 930: /* stuminb */ case 936: /* stuminb */
value = 876; /* --> lduminb. */ value = 882; /* --> lduminb. */
break; break;
case 931: /* stuminh */ case 937: /* stuminh */
value = 877; /* --> lduminh. */ value = 883; /* --> lduminh. */
break; break;
case 932: /* stumin */ case 938: /* stumin */
value = 878; /* --> ldumin. */ value = 884; /* --> ldumin. */
break; break;
case 933: /* stuminlb */ case 939: /* stuminlb */
value = 880; /* --> lduminlb. */ value = 886; /* --> lduminlb. */
break; break;
case 934: /* stuminlh */ case 940: /* stuminlh */
value = 883; /* --> lduminlh. */ value = 889; /* --> lduminlh. */
break; break;
case 935: /* stuminl */ case 941: /* stuminl */
value = 886; /* --> lduminl. */ value = 892; /* --> lduminl. */
break; break;
case 937: /* mov */ case 943: /* mov */
value = 936; /* --> movn. */ value = 942; /* --> movn. */
break; break;
case 939: /* mov */ case 945: /* mov */
value = 938; /* --> movz. */ value = 944; /* --> movz. */
break; break;
case 950: /* sevl */ case 956: /* sevl */
case 949: /* sev */ case 955: /* sev */
case 948: /* wfi */ case 954: /* wfi */
case 947: /* wfe */ case 953: /* wfe */
case 946: /* yield */ case 952: /* yield */
case 945: /* nop */ case 951: /* nop */
value = 944; /* --> hint. */ value = 950; /* --> hint. */
break; break;
case 959: /* tlbi */ case 965: /* tlbi */
case 958: /* ic */ case 964: /* ic */
case 957: /* dc */ case 963: /* dc */
case 956: /* at */ case 962: /* at */
value = 955; /* --> sys. */ value = 961; /* --> sys. */
break; break;
default: return NULL; default: return NULL;
} }

585
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

24
opcodes/aarch64-opc-2.c
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@@ -145,24 +145,24 @@ static const unsigned op_enum_table [] =
697, 697,
703, 703,
704, 704,
741, 747,
742, 748,
743, 749,
744, 750,
12, 12,
510, 510,
511, 511,
936, 942,
938, 944,
940, 946,
748, 754,
939, 945,
937, 943,
259, 259,
499, 499,
509, 509,
508, 508,
746, 752,
505, 505,
502, 502,
495, 495,
@@ -171,7 +171,7 @@ static const unsigned op_enum_table [] =
504, 504,
506, 506,
507, 507,
756, 762,
526, 526,
529, 529,
532, 532,

10
opcodes/aarch64-tbl.h
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@@ -1222,6 +1222,8 @@ static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
static const aarch64_feature_set aarch64_feature_lse = static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
#define CORE &aarch64_feature_v8 #define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp #define FP &aarch64_feature_fp
@@ -1229,6 +1231,7 @@ static const aarch64_feature_set aarch64_feature_lse =
#define CRYPTO &aarch64_feature_crypto #define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc #define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse #define LSE &aarch64_feature_lse
#define LOR &aarch64_feature_lor
struct aarch64_opcode aarch64_opcode_table[] = struct aarch64_opcode aarch64_opcode_table[] =
{ {
@@ -2017,6 +2020,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q}, {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
{"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
{"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q}, {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
/* Limited Ordering Regions load/store instructions. */
{"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
{"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
{"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
/* Load/store no-allocate pair (offset). */ /* Load/store no-allocate pair (offset). */
{"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
{"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF}, {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},