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[ARM] Enable conditional Armv8-M instructions

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Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.

2018-01-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
	and vlstm conditionally executable and reindent parameters.
	* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
	aforementionned instructions.
This commit is contained in:
Thomas Preud'homme
2018-01-15 14:11:02 +00:00
parent df9909b867
commit 2875ce2b55
3 changed files with 27 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@@ -1,3 +1,10 @@
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M

16
gas/config/tc-arm.c
View File

@@ -21457,19 +21457,19 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m
TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
TCE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
TCE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
TCE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
TCE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
TCE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
TCE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
/* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
instructions behave as nop if no VFP is present. */
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m_main
TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn),
TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn),
TCE("vlldm", 0, ec300a00, 1, (RRnpc), 0, rn),
TCE("vlstm", 0, ec200a00, 1, (RRnpc), 0, rn),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT

9
gas/testsuite/gas/arm/archv8m-cmse-main.s
View File

@@ -4,3 +4,12 @@
T:
vlldm r1
vlstm r2
it ne
blxnsne r4
it ne
bxnsne r4
itttt ne
ttane r0, r1
ttane r8, r9
ttatne r0, r1
ttatne r8, r9