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include/opcode/

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* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
	(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
	(MIPS16_INSN_COND_BRANCH): Delete.

opcodes/
	* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
	(WR_SP): Replace with...
	(MOD_SP): ...this.
	(mips16_opcodes): Update accordingly.
	* mips-dis.c (print_insn_mips16): Likewise.

gas/
	* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
	flags for MIPS16 and non-MIPS16 instructions.
	(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
	(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
	(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
	(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
	and non-MIPS16 instructions.  Fix formatting.
This commit is contained in:
Richard Sandiford
2013-08-01 20:40:24 +00:00
parent a8d92fc6c3
commit 265459441c
7 changed files with 81 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
opcodes/mips-dis.c
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@@ -1749,15 +1749,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
/* Figure out branch instruction type and delay slot information. */
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
info->branch_delay_insns = 1;
if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
| MIPS16_INSN_UNCOND_BRANCH)) != 0)
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
|| (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
{
if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
}
else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
info->insn_type = dis_condbranch;
return length;